Semiconductor device packaging assembly

Details Semiconductor device packaging assembly Semiconductor device packaging assembly

2001-01-18

2003-06-10

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With structure for mounting semiconductor chip to lead frame

C257S666000, C257S670000

Reexamination Certificate

active

06576985

ABSTRACT:

FIELD OF INVENTION
The present invention relates to a semiconductor device packaging assembly and method of manufacturing the same, and more particularly, relates to a method for assembling a plurality of semiconductor chips at a time, and the semiconductor chip assemblies formed by the method. By using the method provided in the present invention, the throughput of assembling semiconductor devices can be significantly enhanced.
BACKGROUND OF INVENTION
The “assembly” of a semiconductor device package mentioned in the present invention particularly refers to the procedure of electrically coupling bonding areas, such as bonding pads, of the main surface of a chip to the leadframe, during the process of semiconductor device packaging after the manufacturing of the semiconductor chip.
A conventional assembly of a semiconductor device, please refer to
FIG. 1A
showing the common packaging assembly of a single semiconductor chip, employs the wire bonding method. A plurality of metal wires
11
are bonded between the bonding areas
101
of the chip
100
and the leadframe
102
, for providing the electrical conduction therein. Since the exemplary packaging assembly illustrated in
FIG. 1A
is directed to that of a single semiconductor transistor (in fact, it is the packaging assembly of a power MOSFET), some pins (e.g., PINs
1
-
3
) are connected together and electrically coupled to an electrode (i.e., the drain electrode) of the chip via wires
11
. As for PIN
4
, this pin is connected to another electrode (i.e., the gate electrode) of the chip via a wire.
There are many drawbacks in the conventional semiconductor device packaging assembly as shown in
FIG. 1A
, especially in the aspect of manufacturing efficiency. To improve the manufacturing throughput in mass production, conventional technologies adopt the following approaches. Referring to
FIG. 1B
, a plurality of semiconductor chips are assembled by using a single row of leadframe strip
12
. The leadframe strip
12
comprises many repeated units of leadframes
102
. The fine architecture of the leadframe
102
is not shown in
FIG. 1B
; however, it can be referred to the leadframe
102
in FIG.
1
A. Many chips
100
to be assembled are respectively placed on the leadframes
102
and then, the above-mentioned wire bonding method is applied to those chips to electrically connect each of the bonding pads
101
to the corresponding leadframe via wires
11
. Generally speaking, the method shown in
FIG. 1B
is the one-dimensional extension of the single chip packaging assembly shown in
FIG. 1A
, so that the assembly can be easily adapted to the processing on a production line. In addition, the single row of leadframe strip
12
uses equally spaced sprocket holes
103
consecutively appearing on two edges of the strip
12
, to enhance the alignment or reeling of the leadframe strip
12
. The production efficiency is therefore improved.
To further improve the production efficiency, referring to
FIG. 1C
, the conventional technique extends the one-dimensional, single row leadframe strip of
FIG. 1B
to a two-dimensional, planar leadframe matrix for use in the assembly of many semiconductor chips. However, as shown in
FIG. 1C
, conventional technique still utilizes the wire bonding method to bond wires
11
between each chip
100
and the corresponding leadframe
102
.
Although the above techniques of the semiconductor device packaging assembly, somehow, are gradually improved in the aspect of production efficiency, the effects of improvement on throughput are actually quite limited and there are still many disadvantages left to be overcome in the prior art. The major reason for the disadvantages is due to the constraint set by the wire bonding method. Specifically, as clearly shown in
FIGS. 1A
,
1
B and
1
C, all assembly methods involve the step of bonding a plurality of wires
11
between the leadframes
102
and the bonding areas
101
of the chips. As a result, despite the methods of the single row leadframe strip and planar leadframe matrix, which deal with the semiconductor device packaging assembly in a “multi-tasking” manner, the improvement of production throughput is not significant. Besides, conventional techniques unquestionably will engage all the drawbacks of the wire bonding method, such as bad utilization rate of the whole chip area, poor thermal dissipation of the package, complicated manufacturing processes, low production efficiency and unstability of the package.
There is, thus, a need to provide a highly efficient semiconductor device packaging assembly and method for manufacturing the same, which can assemble a plurality of semiconductor chips at the same time. Such assembly and method can significantly increase the production throughput and also solve the problems caused by the wire bonding method. This invention addresses the need.
SUMMARY OF INVENTION
An object of the present invention is to provide a semiconductor device packaging assembly and method of manufacturing the same, which have simplified manufacturing processes and also can significantly increase the production throughput.
Another object of the present invention is to provide a semiconductor device packaging assembly and method of manufacturing the same, which can efficiently utilize the chip area, and dissipate the heat effectively. The manufacturing processes of the assembly are easy and the stability of the assembly is good.
According to a semiconductor device packaging assembly method of the present invention, which can be used for assembling a plurality of semiconductor chips at a time, the method can enhance the production throughput of the assembly. Said method comprises the steps of: providing a row of a bottom frame strip having a plurality of bottom frame units, each bottom frame unit including a bottom supporting portion and a bottom frame portion; providing a row of a bridge frame strip having a plurality of bridge frame units, each bridge frame unit including a bridge frame portion and a plurality of conducting bars; placing each of the chips on each of the bottom supporting portions, respectively, and attaching the opposite surface of the main surface of each chip to the respective bottom supporting portion; and bonding each bottom frame unit and each bridge frame unit together, wherein, each of the conducting bars extending from each bridge frame portion toward the chip is electrically coupled to the corresponding bonding area of the chip.
According to another semiconductor device packaging assembly method of the present invention, which can be used for assembling a plurality of semiconductor chips at a time, the method can enhance the production throughput of the assembly. Said method comprises the steps of: providing a bottom frame matrix having a plurality of bottom frame units, each bottom frame unit including: a bottom supporting portion and a bottom frame portion; providing a bridge frame matrix having a plurality of bridge frame units, each bridge frame unit including: a bridge frame portion and a plurality of conducting bars; placing each of the chips on each of the bottom supporting portions, respectively, and attaching the opposite surface of the main surface of each chip to the respective bottom supporting portion; and bonding each bottom frame unit and each bridge frame unit together, wherein, each of the conducting bars extending from each bridge frame portion toward the chip is electrically coupled to the corresponding bonding area of the chip.
Because the above semiconductor device packaging assembly methods employ bridge frame units having conducting bars for providing the electrical connection between the leadframes and the chips, rather than employing the wire bonding approach, the manufacturing processes in the present invention are no longer complicated and time-consuming. While assembling a plurality of semiconductor chips at a time, the present invention can significantly increase the throughput of assembly and achieve a much better effect than the conventional wire bonding technique.
Furthermore, bec

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