Semiconductor device package substrate probe fixture

Details Semiconductor device package substrate probe fixture Semiconductor device package substrate probe fixture

2001-06-19

2004-07-06

Cuneo, Kamand (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S757020

Reexamination Certificate

active

06759860

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to electronic testing and, more particularly, to testing of packaged integrated circuit subsystems.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Until recently, the ongoing quest of the semiconductor industry was to improve the performance of integrated circuits (“ICs”) either before or after the integrated circuit was placed in a package and hermetically sealed from the elements. However, advancements in the performance in integrated circuits are now being limited by the technology by which the circuits are packaged. Efficient packaging of integrated circuits involves increasing the package density (i.e., pin-out) and package performance (i.e., electrical conductance and signal speed).
There are several packaging technologies developed to connect integrated circuits to a substrate. For example, the circuit can be coupled using through-hole wire bonding or soldering. Alternatively, the circuit can be bonded using surface mount technology, tape automated bonding, and flip-chip bonding. The drive for more densely configured integrated circuits has lead to an increased pin-out of input/output pads per circuit area. Flip-chip package technologies such as chip scale packaging and direct chip attach have evolved to handle the higher density pad configuring by arranging the pads in an array across the surface topography. The pads can be placed nearing the core logic of the circuit and/or whatever subsystem that involves their use to minimize capacitive coupling and thereby flip chip technology adds to the overall performance of the circuit.
The array of bonding pads are arranged in a two-dimensional array of rows and columns upon a frontside surface of the circuit. Attachment of the array of pads to an underlying board, using the flip chip configuration, involves inverting the circuit so that the frontside surface with the bonding pads faces downward onto a package substrate, which has corresponding set of bonding pads. The circuit and/or board is then heated and a solder connection is formed at the interface between the integrated circuit bonding pads and the bonding pads of the board. When the solder cools and hardens, the I/O pads of the circuit are electrically and mechanically coupled to the bonding pads of the printed circuit board. The printed circuit board, or “board,” includes printed conductors extending across the upper, lower or buried surfaces of the board. One or more trace conductors can extend upward from a plane on which multiple trace conductors are formed through vias which contact with the bonding pads. To minimize the mechanical strain on the solder bump attachments due to the coefficient of thermal expansion mismatch between the substrate material of the board and the integrated circuit, an underfill material, which is typically a thermosetting polymer (e.g., an epoxy resin) may be dispensed in liquid form between the IC and the substrate which subsequently hardens and securely encapsulates the solder bumps which form at the interface of the integrated circuit bonding pads and the substrate bonding pads.
A well-suited package substrate for a flip-chip application is a ball grid array (“BGA”) substrate. A BGA package substrate may be made of, for example, fiberglass-epoxy printed circuit board material or a ceramic material (e.g., aluminum oxide, alumina, Al
2
O
3
, or aluminum nitride, AlN), and it may be a single layer or a multi-layer fabricated substrate. In a flip-chip design application, the substrate includes two sets of bonding pads: a first set adjacent to the chip and a second set on a surface of the substrate opposite the first set. Accordingly, both sets are arranged in a two-dimensional array across the upper and lower surface of the device package. The substrate may include multiple layers of a patterned conductive material forming electrical conductors. Interlayer vias may be formed by precise drilling for electrical and thermal routing through the substrate. The configuration of interlayer vias and intra-layer patterned electrical conductors results in trace conductors that electrically connect members of the first and second sets of bonding pads. Members of the first set of bonding pads on the upper surface can be solder bump attached to corresponding I/O bonding pads of the inverted integrated circuit, i.e., “flip chip.” Members of the second set of bonding pads function as device package terminals, and are coated with solder. The second set of bonding pads of overcoated solder on the underside of the BGA device package allow the substrate (and trace conductors contained therein connected to corresponding I/O bonding pads) to be surface mounted to a larger printed circuit board (e.g., a motherboard). During board assembly, the BGA package is attached to the corresponding bonding pads on the board using standard reflow techniques.
Device failure or performance impairment can occur in these packaged devices if a trace conductor or a group of trace conductors are not properly conducting electrical signals to or from the attached chip. A large electrical resistance measured across a trace conductor may indicate that there is an open or break in the conductive pathway of the trace conductors. There are several ways that this can occur either at the terminal sites or along the length of the trace conductor. The solder balls or solder bumps could have been improperly attached, or experienced critical mechanical strain due to the coefficient of thermal expansion or package mishandling. There could be micro-cracks or other breaks in the terminals or in the trace conductors inside the substrate. There could be manufacturing defects such as, incomplete vias, missing vias, or misaligned vias between the substrate layers. Further, electromigration could cause cracks to form in the solder joints or in the trace conductor line inside the substrate, etc.
To test and locate the exact source of a break in the electrical continuity of a trace conductor requires the destructive dismantling of the package and is typically a final step in failure analysis of such devices. A trace conductor or group of trace conductors will first be pinpointed as a source of an electrical pathway conductivity problem from prior failure analysis tests. A current method for testing the electrical continuity of the trace conductors of the BGA flip-chip package substrates involves first removing the semiconductor chip so as to expose the solder bumps encapsulated in the underfill material beneath the inverted integrated circuit. An electrical testing device such as a multi-meter can then be used to measured the resistance of the trace conductor by connecting the two probe wires of the meter on either end of the trace conductor. Typically, a probe wire is soldered to the trace conductor solder ball terminal on the underneath side of the board. The other probe wire may have a probe needle attached for making electrical contact with the exposed solder bump at the upper surface of the board.
If the resistance measured is defect-level high (a value that is dependent on substrate design), then typically a subsequent upper layer of the substrate is removed by a parallel lapping process, which may be performed by a polishing grinding wheel. Removing the upper layer of the substrate entails removing the solder bumps that lie just beneath the removed integrated circuit. Another resistance probe measurement would be taken. Again if the resistance measured is high, another upper layer can be removed and the measuring procedure repeated on the lower layers until the layer having the defect is found. However, problems can arise using this testing method. The defect may be heat-cured during the solder attachment of the probe wire to the solder ball if the defect is physically located at or in proximity of the solder ball. The subsequent removal of upper substrate layers during the parallel lapping process can put und

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