Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
1998-03-20
2001-01-16
Tran, Minh Loan (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S778000, C257S685000, C257S686000, C257S789000, C257S758000, C257S737000, C257S779000, C257S770000, C257S784000, C438S108000, C438S109000
Reexamination Certificate
active
06175157
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device having a plurality of semiconductor chips. More particularly, this invention relates to a semiconductor device having one semiconductor chip stacked thereon with another semiconductor chip so that they are connected together, thereby increasing the integration density.
2. Description of the Prior Art
There is one example of this kind of a conventional semiconductor device disclosed by Japanese Laying-Open Patent Publication No. H6-112402 [H01L25/065, 07, 18] assigned to the same assignee as this invention was assigned to. This prior art includes two IC chips each having bumps formed at a periphery of a connecting surface so that the two IC chips are connected together. These both IC chips are further transfer-molded into a mold or package.
In this prior art, however, the bumps are placed only at the periphery of the IC chip, involving a problem as stated below. That is, no bumps are provided at a central area of the IC chips so that a gap might occur between the central areas of the two IC chips. This results in warping in at least one of the two IC chips in a manner of nearing two IC chips together. Accordingly, there arises a problem that the circuit elements formed in the connection surface undergo damage due to nearing the two IC chips, besides the warped IC chip surface suffers from cracks. This tendency becomes prominent as the area of the IC chips increases.
SUMMARY OF THE INVENTION
Therefore, it is a primary object of this invention to provide a novel semiconductor device having a plurality of semiconductor chips.
It is another object of this invention to provide a semiconductor device that can prevent the semiconductor chip from warping.
It is further object of this invention to provide a semiconductor device having semiconductor chips and circuit elements prevented from being damaged.
A semiconductor device according to this invention, comprises: a first semiconductor chip having a first connecting surface; a second semiconductor chip placed over the first semiconductor chip and having a second connecting surface; a plurality of first bumps formed on at least one of the first connecting surface and the second connecting surface so as to connect between the first semiconductor chip and the second semiconductor chip; and at least one second bumps formed at least one of the first connecting surface and the second connecting surface.
The first bumps serve to connect between the first connecting surface and the second connecting surface, i.e., the first semiconductor chip and the second semiconductor chip. The second bumps are interposed, at an area other than that having the first bumps, between the first semiconductor chip and the second semiconductor chip. Therefore, even if a warp occurs in one or both of the first semiconductor chip and the second semiconductor chip, the deformation is suppressed to a minimum extent.
Therefore, according to this invention, it is possible to prevent the semiconductor chip from excessively warping so that there is no possibility of damaging to the semiconductor chip or circuit elements formed thereon.
Incidentally, the first bumps solely may be utilized to connect between the first semiconductor chip and the second semiconductor chip. Alternatively to this, both the first bumps and the second bumps may be used for the connection. Note that the first bump (and the second bump) serving to connect between chips is referred to as “connecting bump” while the second bump not serving to connect between the chips is referred to as “dummy bump” throughout this Specification.
REFERENCES:
patent: 4764804 (1988-08-01), Sahara et al.
patent: 5120665 (1992-06-01), Tsukagoshi et al.
patent: 5376825 (1994-12-01), Tukamoto et al.
patent: 5400950 (1995-03-01), Myers et al.
patent: 5523628 (1996-06-01), Williams et al.
patent: 5686703 (1997-11-01), Yamaguchi
patent: 5734199 (1998-03-01), Kawakita et al.
patent: 5813870 (1998-09-01), Gaynes et al.
patent: 362150837 (1987-07-01), None
patent: 401185952 (1989-07-01), None
patent: 407050330 (1995-02-01), None
Hoffmann & Baron , LLP
Rohm & Co., Ltd.
Thai Luan
Tran Minh Loan
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