Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Beam leads
Reexamination Certificate
2001-10-26
2002-08-13
Clark, Jasmine J B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Beam leads
Reexamination Certificate
active
06433424
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor device packages and more specifically relates to a novel package in which mechanical stresses on the semiconductor die are reduced.
BACKGROUND OF THE INVENTION
Semiconductor devices are well know, in which a thin brittle silicon die is secured to a lead frame by soldering or through the use of a conductive or non-conductive adhesive such as an epoxy. The lead frame, which is conventionally a conductive metal such as a thin flat plated copper alloy strip will have a large number of identical patterns stamped in the strip. The patterns provide enlarged pad areas to which a respective die can be secured, and a plurality of integral terminal sections or leads, or “pins”, subsequently isolated from the pad, which receive wire bonds from leads to electrodes on the top surfaces of the die. After wire bonding, the individual lead frame device sections are over-molded with a suitable plastic housing. The individual packages are next separated and the various terminals are isolated from one another with the leads or pins from the terminal sections and pad connectors extending through the housing wall to permit electrical connection to the die housed within the package.
The pad receiving the silicon die in the past is always of larger area than the die, so that the full bottom surface of the die is rigidly connected to the pad surface. Since the silicon die and metal or other pad substrate have different coefficients of thermal expansion, the die, during soldering or other heat producing attachment processes, and during thermal cycling while in test or in operation, causes mechanical stress over the full surface area of the die. These stresses can cause damage to or breakage of the die.
BRIEF DESCRIPTION OF THE INVENTION
In accordance with the invention, the silicon die is dimensioned such that the die is larger than the die receiving pad, in at least one and preferably in all directions. Consequently, a smaller portion of the area of the die is connected rigidly to the pad, and the total stress applied to the die is reduced.
In a preferred embodiment, at least two small area but overhanging die are used with two even smaller respective area pads. Thus, the two die will have the same total area as a single die which may have been previously used, and both have a reduced pad area contact. Consequently, stress on the two (or more) die is substantially reduced.
In a preferred embodiment of the invention, two overhanging MOSFET die may be employed for a 6 lead TSOT type package. The die can be interconnected as desired (in parallel or series arrangement). Other device die combinations, for example, a MOSFET die and a Schottky diode die could also be placed in a common package, both overhanging their respective lead frame pads.
A significant advantage of the invention is that it permits the housing of significantly larger silicon die area in a standard outline plastic package without increasing the outline dimensions.
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International Search Report dated Apr. 4, 2002 from the International Searching Authority for corresponding PCT Appln. No. PCT/US01/46676.
Clark Jasmine J B
International Rectifier Corporation
Ostrolenk Faber Gerb & Soffen, LLP
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