Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2008-07-18
2010-12-07
Fahmy, Wael M (Department: 2814)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C257S773000, C257SE23170, C257SE21585, C257SE21499, C257SE21519, C438S106000, C438S055000
Reexamination Certificate
active
07846777
ABSTRACT:
A semiconductor device package and fabricating method thereof are disclosed, by which heat-dissipation efficiency is enhanced in a system by interconnection (SBI) structure. An exemplary semiconductor device package may include a substrate, at least two chips mounted on the substrate to have a space between one or more of the chips and an edge of the substrate, an insulating layer covering the chips, the insulating layer having via holes exposing portions of the at least two chips and a trench between the via holes, the insulating layer having at least two hole patterns within the space, and a metal layer filling the via holes and the trench.
REFERENCES:
patent: 5250843 (1993-10-01), Eichelberger
patent: 5366906 (1994-11-01), Wojnarowski et al.
patent: 2003/0011049 (2003-01-01), Nuytkens et al.
patent: 2005/0254215 (2005-11-01), Khbeis et al.
Armand Marc
Dongbu Hitek Co., Ltd.
Fahmy Wael M
Workman Nydegger
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