Semiconductor device package

Active solid-state devices (e.g. – transistors – solid-state diode – Bulk effect device – Intervalley transfer

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Details

257700, 257738, 257780, 438613, H01L 2348, H01L 2352, H01L 2940, H01L 2312

Patent

active

058616705

ABSTRACT:
An integrated circuits package or a chip carrier having an integrated circuits chip sealed therein comprises layers of ceramic substrates, and terminal steps which are connected to inner pads in contact with the integrated circuits chip and which are provided on the bottom surface of at least one layer of the package, preferably the lowermost layer. The terminal steps are provided in a lattice arrangement, with so many rows of terminal steps as equals the number of terminal steps in one row, thus enabling connection of all of the terminals of the chip to outside wirings, such as wirings of a mother board.

REFERENCES:
patent: 3489845 (1970-01-01), Landron
patent: 3617817 (1971-11-01), Kawakatsu
patent: 3700788 (1972-10-01), Spurk
patent: 3729820 (1973-05-01), Ihochi et al.
patent: 3730969 (1973-05-01), Buttle et al.
patent: 4082394 (1978-04-01), Gedney et al.
patent: 4193082 (1980-03-01), Dougherty
patent: 4288841 (1981-09-01), Gogal
"Bumps and Balls, Pillars and Beams: a Survey of Face-Bonding Methods" George Sideris, Electronics Jun. 28, 1965 pp. 68-69.
"Distribution System for Multilayer Ceramic Modules" Z. Markewycz, IBM Technical Disclosure Bulletin vol. 19, No. 4, Sep. 1976, pp. 1270-1271.
IBM Technical Disclosure Bulletin, vol. 15, No. 6, pp. 1977-1980, Nov. 1972, "Packaging of Integrated Circuits" C. M. McIntosh and A.F. Schmeckenbecher.

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