Semiconductor device manufacturing: process – Semiconductor substrate dicing
Reexamination Certificate
2005-05-24
2005-05-24
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Semiconductor substrate dicing
C438S461000, C438S462000, C438S463000, C438S113000, C438S033000
Reexamination Certificate
active
06897127
ABSTRACT:
A wiring pattern is formed over a semiconductor wafer, and an external terminal is formed on the wiring pattern. The wiring pattern extends from a pad which is part of an interconnect to an integrated circuit formed in the semiconductor wafer. A non-resin layer of a non-resin material is formed in a first region of the semiconductor wafer. A resin layer is formed in a second region which is a region of the semiconductor wafer other than the first region by utilizing the non-resin layer. The semiconductor wafer is cut long the first region.
REFERENCES:
patent: 6633081 (2003-10-01), Sahara et al.
patent: A 11-297873 (1999-10-01), None
U.S. Appl. No. 10/667,331, filed Sep. 23, 2003, Hanaoka
U.S. Appl. No. 10/679,467, filed Oct. 7, 2003, Hanaoka.
U.S. Appl. No. 09/700,464, filed Nov. 15, 2000, Hanaoka et al.
Le Dung A.
Oliff & Berridg,e PLC
Seiko Epson Corporation
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