Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Encapsulating
Reexamination Certificate
2001-05-16
2002-12-24
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Encapsulating
C257S687000, C257S697000
Reexamination Certificate
active
06498055
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims benefit of priority under 35 U.S.C. § 119 to Japanese Patent Application No. 2000-145453, filed on May 17, 2000, the entire contents of which is incorporated by reference herein.
DETAILED DESCRIPTION OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device, a method of manufacturing a semiconductor device, a resin molding die, and a semiconductor manufacturing system, and more particularly relates to a semiconductor device in which at least one semiconductor element (e.g. a semiconductor chip) is encapsulated in a resin seal, a method of manufacturing such a semiconductor device, a resin molding die used in the methods, and a semiconductor manufacturing system for carrying out the foregoing semiconductor device manufacturing method.
2. Description of Related Art
Semiconductor devices having the ball grid array structure are well-known at present. Referring to FIG.
25
and
FIG. 26
of the accompanying drawings, such a semiconductor device comprises: a substrate
1
made of a resin, a tape, ceramics or the like and having a wiring circuit formed thereon; a semiconductor chip
2
fixedly mounted on the substrate
1
using an adhesive layer
3
; a bonding wire
5
, e.g. a gold bonding wire, connecting a bonding pad of the semiconductor chip
2
and a wiring circuit terminal
4
on the substrate
1
; and a resin seal
6
for encapsulating the semiconductor chip
2
. A resin gate scar
6
G via which resin was injected for the transfer molding process remains on a side surface of the resin seal
6
. External connection terminals
8
constituted by solder balls are electrically connected to the wiring circuit terminal
4
on the rear surface of the substrate
1
.
FIG.
27
and
FIG. 28
show a cavity-down type semiconductor device having the ball grid array structure. The semiconductor device comprises: a substrate
1
made of a resin, a tape, ceramics or the like and having a wiring circuit and a through-hole on the center thereof; a metal plate
10
or an insulated plate
10
stuck onto the substrate
1
by an adhesive layer
9
; a semiconductor chip
2
fixedly attached by an adhesive layer
3
in a recess defined by the through-hole in the substrate
1
and the plate
10
; a bonding wire
5
, e.g. a gold bonding wire, connecting a bonding pad of the semiconductor chip
2
to a wiring circuit terminal
4
on the rear surface of the substrate
1
; and a resin seal
6
encapsulating the semiconductor chip
2
. A resin gate scar
6
G via which resin was injected for the transfer molding process remains on a side surface of the resin seal
6
. External connection terminals
8
constituted by solder balls are electrically connected to the wiring circuit terminal
4
on the rear surface of the substrate
1
, i.e. where the wiring circuit terminal
4
is provided.
The semiconductor device of FIG.
25
and
FIG. 26
is resin molded as shown in FIG.
29
A and
FIG. 29B. A
resin molding die including upper and lower dies
11
and
12
is heated to a temperature of approximately 165° C. to 185° C. Thereafter, a resin tablet or powder
14
is supplied to a pot
13
in the lower die
12
. The substrate
1
, on which the semiconductor chip
2
and the bonding pad of the semiconductor chip
2
are provided and is connected to the wiring circuit terminal
4
using the gold bonding wire
5
, is placed between the upper and lower dies
11
and
12
. In this state, the upper and lower dies
11
and
12
are clamped as shown in FIG.
29
A. The resin
14
in the pot
13
is pressurized using a plunger
15
and melted, and is injected into a cavity
17
via a runner
16
and the resin gate
7
. The resin
14
is left as it is for approximately 40 seconds to 180 seconds, and is hardened in order to form the resin seal
6
. Thereafter, the upper and lower dies
11
and
12
are unclamped, so that the resin seal
6
is removed from the upper and lower dies
11
and
12
. By this, the semiconductor device is almost completed. The resin seal
6
includes superfluous resins
14
A such as a cull
18
, runner
17
and resin gate
7
formed when injecting the resin
14
, which are removed by the gate-breaking, and are discharged.
In order to facilitate the peeling of the unnecessary resin
14
A in the gate-breaking, a metal part
19
is sometimes provided over the runner
16
and resin gate
7
on the substrate
1
, as shown in FIG.
30
.
In the semiconductor device of FIG.
27
and
FIG. 28
, the resin seal
6
is at the center of the rear surface of the substrate
1
, and is surrounded by the external connection terminals
8
. Therefore, if the runner
16
extends over a part of the external connection terminals
8
(solder balls), a part of the surplus resin
14
A may stick on them. Some surplus resin
14
A may scrape a part of external connection terminals
8
which are being formed. Any of resin molding processes shown in
FIG. 31
to
FIG. 34
is utilized in order to overcome this problem.
In a first resin molding process shown in
FIG. 31
, a resin is injected with a third die or a plate
20
inserted between upper and lower dies
11
and
12
. Specifically, the third die or plate
20
extends all over the external connection terminals
8
on the rear surface of the substrate
1
, so that the resin cannot stick onto the external connection terminals
8
.
According to a second resin molding process shown in
FIG. 32
, the resin is injected with a sheet
21
such as a film sandwiched between the upper and lower dies
11
and
12
. Similarly to the third die or plate
20
, the sheet
21
extends all over the external connection terminals
8
on the rear surface of the substrate
1
, which can prevent the resin from sticking onto the external connection terminals
8
.
A third resin molding process shown in
FIG. 33
is described in Japanese Patent Laid-Open Publication No. Hei 7-221132, for example. In this method, a resin inlet
22
is in the shape of a recess and extends between the pot
13
in the lower die
12
and the plate
10
connecting to the pot
13
. Further, a resin outlet
23
extends to the cavity
17
from the resin inlet
22
. The resin
14
in the pot
13
is pushed upward using a plunger
15
in order to fill the cavity
17
via the resin inlet
22
and the resin outlet
23
. Both the resin inlet
22
and the resin outlet
23
are formed in the substrate
1
. Since no resin
14
passes over the external connection terminals
8
, it is possible to prevent the resin
14
from sticking onto the external connection terminals
8
.
A fourth resin molding process is similar to the third method. However, the fourth method is applied to a cavity-up type semiconductor device as shown in FIG.
34
. This semiconductor device comprises: a substrate
1
made of a resin, a tape, ceramics or the like and having a wiring circuit provided thereon; a frame
24
made of a metal plate or an insulated plate, having a through-hole at the center thereof and stuck onto the front surface of the substrate
1
using an adhesive layer
25
; a semiconductor chip
2
fixedly attached using an adhesive layer
3
in a recess defined by the substrate
1
and the through-hole in the frame
24
; a bonding wire
5
, e.g. a gold bonding wire, connecting a bonding pad of the semiconductor chip
2
to a wiring circuit terminal
4
on the front surface of the substrate
1
; and a resin seal (not shown) encapsulating the semiconductor chip
2
. In this method, a resin inlet
22
in the shape of a recess is formed in the frame
24
and around the semiconductor chip
2
and is connected to the pot
13
provided in the lower die
12
. Further, a resin outlet
23
extends from the resin inlet
22
to the cavity
17
. The resin
14
in the pot
13
is pushed upward by the plunger
15
, and injected into the cavity
17
via the resin inlet
22
and the resin outlet
23
. Both the resin inlet
22
and the resin outlet
23
are formed in the substrate
1
, so that no resin
14
passes over the external connection terminals
8
. This is effe
Fukuda Masatoshi
Harada Susumu
Nakano Atsushi
Sato Hidenobu
Sato Tetsuya
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Ho Tu-Tu
Kabushiki Kaisha Toshiba
Nelms David
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