Semiconductor device, method of generating pattern for...

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics

Reexamination Certificate

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Details

C257S202000, C257SE21423, C257SE21679, C257SE27103, C257SE29309

Reexamination Certificate

active

07911027

ABSTRACT:
It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit.The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.

REFERENCES:
patent: 5012309 (1991-04-01), Nakayama
patent: 5635736 (1997-06-01), Funaki et al.
patent: 6204542 (2001-03-01), Kinoshita et al.
patent: 6434730 (2002-08-01), Ito et al.
patent: 7307333 (2007-12-01), Itoh et al.
patent: 2003/0011007 (2003-01-01), Takashino
patent: 2003/0185068 (2003-10-01), Saito et al.
patent: 8-88356 (1996-04-01), None
patent: 11-31819 (1999-02-01), None
patent: 2000-208634 (2000-07-01), None
patent: 2000208634 (2000-07-01), None
patent: 2001-189420 (2001-07-01), None
Japanese Office Action, with English translation, issued in Japanese Patent Application No. JP 2001-356279, mailed Jan. 9, 2008.

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