Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
2001-02-28
2003-01-21
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S063000, C257S065000, C257S327000, C257S616000
Reexamination Certificate
active
06509586
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device of a MIS (Metal-Insulator-Semiconductor) structure and a method for fabricating the same, more specifically to a semiconductor device and a method for fabricating the same which can decrease parasitic resistance and improve current-driving performance.
The present invention also relates to a semiconductor device of semiconductor-semimetal structures, and a semiconductor integrated circuit including a plurality of the semiconductor integrated structures laid one on another through inter-layer insulation films.
Semiconductor devices require higher integration and higher speed for further improved performances. To meet such requirements, micronization of constituent elements is essential. Not only micronizing techniques, but also various structures and their fabrication methods for attaining high operation speed of the elements are proposed.
In a transistor of MIS (Metal-Insulator-Semiconductor) structure, which represents MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the element is micronized mainly by decreasing the gate length.
However, as the MOSFET is more micronized, the influence of the drain electric field to the channel region become unignorable, and the phenomena that a threshold voltage rapidly changes with respect to a gate length, the so-called short channel effect becomes a problem. Generation of the short channel effect causes threshold voltage deviation of an ultra-micronized MOSFET, which substantially decreases margins of circuit designs. In addition, with the element micronization, the dopant diffused layer has become extremely shallow. The parasitic resistance component in the source/drain region is a barrier to improving the current-driving performance.
Accordingly, to develop elements, it is very important to suppress the short channel effect accompanying the element micronization and decrease the parasitic resistance.
FIG. 29
shows a diagrammatic sectional view of the typical MIS-type semiconductor device. An SOI substrate is formed of a silicon substrate
200
, a silicon oxide film
202
formed on the silicon substrate
200
, and a silicon layer
204
formed on the silicon oxide film
202
. A gate electrode
208
is formed on the silicon layer
204
interposing a gate insulation film
206
therebetween. A source/drain diffused layers
210
are formed in the silicon layer
204
on both sides of the gate electrode
208
. The source/drain diffused layers
210
have respective extension regions
214
directed to a channel region
212
, which is immediately below the gate electrode
208
.
The semiconductor device shown in
FIG. 29
suppress the short channel effect by using the SOI substrate and providing the extension regions
214
in the source/drain diffused layers
210
. The extension regions
214
have higher dopant concentration than the lightly doped diffused region of the conventional LDD (Lightly Doped Drain) structure, whereby the source/drain diffused layers
210
has reduced parasitic resistance. However, as the micronization further goes on, even in the semiconductor device shown in
FIG. 29
the parasitic resistance of the source/drain diffused layers will be a barrier factor for improving current-driving performance. This structure is being approaching to the limit in terms of processing techniques because further micronization requires the source/drain diffused layers
210
to have abrupt profile.
On the other hand, it is theoretically presumed that SiGeC semiconductor material, which lattice-matches with the silicon substrate, has the band gap narrowed by increasing a carbon (C) concentration and, furthermore, semimetalized (refer to, e.g., M. Ohfuti et al., Extended Abstracts of the 1999 International Conference on Solid State Device and Materials, Tokyo, 1999, pp. 476-477). Then, it is proposed that such semimetalized layer is used in the so-called elevated source/drain structure so as to decrease parasitic resistance (refer to, e.g., Laid-open Japanese Patent Application No. Hei 11-284171, 1999. As exemplified in
FIG. 30
, in a semiconductor device having an elevated source/drain structure, a semimetal layer
216
of an SiGeC layer is formed on a silicon layer
204
of the source/drain regions. However, in this structure, the semimetal layer
216
is formed across a sidewall insulation film
218
on the side wall of the gate electrode
208
, whereby resistance between a channel region
212
immediately below the gate electrode
208
and the semimetal layer
216
cannot be decreased.
Tucker et al. propose a Schottky junction source/drain structure using a metal layer as the extension regions for the end of decreasing the parasitic resistance in source/drain regions. As shown in
FIG. 31A
, a semiconductor device having the Schottky junction source/drain structure has the source/drain regions formed of a metal layer
220
which is extended down to a channel region
212
immediately below the gate electrode
208
. However, in this structure, potential barrier is formed due to the semiconductor-metal junction (Schottky junction) formed between the channel region
212
and the source/drain regions
220
, whereby the potential in the channel region increases, and excess resistance is generated. This structure cannot be absolutely good for improving current-driving performance. It is also a disadvantage that in order to nullify the potential, an offset voltage is needed until current starts to flow.
As described above, various structures have been proposed so as to decrease the parasitic resistance in the source/drain regions. However, these structures cannot be sufficient to improve current-driving performance. A semiconductor device which can decrease the parasitic resistance in the source/drain diffused layer regions and further improve current-driving performance has been required.
On the other hand, semiconductor integrated circuits have so far continuously increased integration by scale-down of dimensions and break-through of device structures. However, the micronization of transistors has come to the stage of sub-0.1 micron size, and it has come almost to a limit to maintain the scaling. The limit is conspicuous specifically in processing techniques which cause characteristic deflections, such as gate length deflections, dopant deflections, etc., and in thinning ion-doped layers. Furthermore, it is difficult to continue the micronizing trend, e.g., maintain cell size factors of DRAMs and others as far as the micronization trend relies on the conventional planar device structure.
Presently, for further micronization, the so-called vertical MOS transistor has begun to be proposed (refer to e.g., J. M. Hergenrother et al., IEDM Tech., Dig., p. 75, 1999).
However, a transistor simply formed in a vertical structure can have a decreased gate length but must have a large heavily doped semiconductor region in a lead part from the lower region of the gate electrode to the source/drain electrodes. This causes a problem that parasitic, resistance component in this region is a cause for deteriorating high speed and high frequency characteristics of the transistor.
Furthermore, micronizing elements, retaining their high performances is required not only by simple MOS transistors, but also naturally by semiconductor devices of complicated constitutions including a plurality of transistors having different conduction types, dopant concentrations, etc. connected to one another. Further improvement and development of transistor structures are presently waited.
Higher density of integrated circuits and higher integration and higher performances of systems on chips, etc. are required, and multi-layer interconnection techniques and furthermore three-dimensional integration are being studied (refer to, e.g., M. Koyanagi et al., IEEE MICRO 18(4), p.17, 1998).
As exemplified in
FIG. 32
, such integrated circuit comprises LSI chips
301
formed in semiconductor integrated structures, which are arranged in multi-layers one on another with inter-layer insulation film
Fujitsu Limited
Lee Eddie
Richards N. Drew
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