Semiconductor device memory cell and method for selectively eras

Details Semiconductor device memory cell and method for selectively eras Semiconductor device memory cell and method for selectively eras

1999-06-29

2000-08-08

Phan, Trong

Static information storage and retrieval

Floating gate

Particular biasing

365 63, G11C 1134

Patent

active

061011304

ABSTRACT:
An electrically erasable programmable read only memory (EEPROM) array (30) that includes rows and columns of memory cells. Word lines (WL0 and WL1) are substantially parallel to each other and extend in a first direction. Drain bit lines (BL0-B13) and source lines (SL0 and SL1) are substantially parallel to each other and extend in a second direction that is perpendicular to the first direction. The source line (SL0) and source regions of at least two memory cells (31 and 36) within the EEPROM array are electrically connected by a first source local interconnect (LI1). The first source local interconnect (LI1) has a length that extends substantially in the first direction and electrically connects some, but not all, of the memory cells lying within the EEPROM array (30).

REFERENCES:
patent: 4408306 (1983-10-01), Kuo
patent: 5047981 (1991-09-01), Gill et al.
patent: 5339279 (1994-08-01), Toms et al.
patent: 5357476 (1994-10-01), Kuo et al.

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