Coating apparatus – Gas or vapor deposition
Reexamination Certificate
1997-05-30
2001-01-16
Beck, Shrive (Department: 1763)
Coating apparatus
Gas or vapor deposition
C438S004000, C438S029000, C438S025000, C414S935000, 36, 36, C156S345420
Reexamination Certificate
active
06174375
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device manufacturing system.
2. Description of the Related Art
In a method for manufacturing semiconductor devices (wafers), when a new process condition is introduced or a new equipment is introduced, some wafers of a lot are subjected to new process conditions or new equipment, while other wafers of this lot are subjected to the old processes or old equipment. For example, when new ion implantation equipment is introduced, the new ion implantation equipment is used on 10 wafers of a lot, while the old ion implantation equipment is used on 40 wafers of this lot. Thus, branching and merging of wafers are required.
In a prior art method for branching and merging wafers of a lot, the operator searches wafer numbers and branches some of the wafers manually by using vacuum tweezers. Then, the operator sets a new process in the semiconductor device manufacturing equipment in accordance with a manuscript or the like to perform the new process upon the branched wafers. Then, the operator merges the branched wafers with the other wafers by using the vacuum tweezers.
In the above-mentioned prior art wafer branching and merging method, however, since the operation therefor is manually carried out, a long operating time is required. Also, since the operation is carried out by using the vacuum tweezers, the wafers may be damaged which reduces the manufacturing yield. Further, since the operation is carried out by using a manuscript or the like, the operation may become inaccurate and be carried out incorrectly.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device manufacturing system capable of automatic branching and merging of wafers.
According to the present invention, in a semiconductor device manufacturing system including a plurality of semiconductor device manufacturing equipment, a control circuit is connected to the semiconductor device manufacturing equipment. Also, a lot status memory for storing the status of lots of semiconductor wafers, a branch content memory for storing branch information of the lots of semiconductor wafers, and a determination level memory for storing determination levels of the lots of semiconductor wafer are connected to the control circuit.
Thus, the branching and merging of wafers can be carried out in accordance with the contents of the lot status memory, the branch content memory and the determination level memory.
REFERENCES:
patent: 5164905 (1992-11-01), Iwasaki et al.
patent: 5389769 (1995-02-01), Yamashita et al.
patent: 5930137 (1999-07-01), Togashi
patent: 5930138 (1999-07-01), Lin et al.
patent: 6-176994 (1994-06-01), None
Sada Toshihiro
Toyota Hideo
Beck Shrive
Foley & Lardner
NEC Corporation
Torres Norca L.
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