Data processing: generic control systems or specific application – Specific application – apparatus or process – Product assembly or manufacturing
Reexamination Certificate
2001-03-23
2002-02-19
Grant, William (Department: 2121)
Data processing: generic control systems or specific application
Specific application, apparatus or process
Product assembly or manufacturing
C702S185000, C716S030000, C438S015000
Reexamination Certificate
active
06349240
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device manufacturing system for determining the cause of failures in a semiconductor device which has become faulty after the division of a wafer into a plurality of chips, and also to a method of manufacturing semiconductor devices as well as a failure analyzing device.
2. Description of the Related Art
In recent years, the life cycle of electronic devices has been becoming shorter and shorter, and it has become imperative for developers to complete the designs of such electronic devices in a short period of time and to supply them to the market in a timely fashion. While the performance of semiconductor devices mounted in electronic equipment has been improved and the goal of obtaining a higher integration of circuits on a chip has been substantially achieved, a further reduction in the cost of such semiconductor devices is also an objective.
Semiconductor devices are usually manufactured by subjecting a semiconductor wafer to predetermined processing steps (wafer process) by means of several tens of types of manufacturing devices (hereinafter called collectively as “a manufacturing line”). In order to supply semiconductor devices stably at low cost, the number of non-defective products obtained from one sheet of wafer (hereinafter referred to as “yield”) or its rate (hereinafter referred to as “yield rate”) must be raised.
In general, the manufacturing devices are complicated in their construction and include many factors causing the yield rate to be lowered. Also, the yield rate will largely depend on how the manufacturing devices are used and the set conditions for the processing steps.
When starting mass-production of newly developed semiconductor devices or when adding a new manufacturing device to the manufacturing line, the manager of the manufacturing line analyses causes of failures and improves the manufacturing line and the processing steps in an effort to attain a desired yield rate.
Even after the desired yield rate has been attained, the manager of the manufacturing line endeavors to maintain a stable yield rate by always monitoring the manufacturing line in order to detect in advance any sign of a deteriorating yield rate.
Thus, unless the development of the processing steps necessary for the high-degree integration of circuits and the stabilization of such processing steps have been completed as quickly as possible, it is quite difficult to ship the needed semiconductor devices stably within an acceptable time period.
Therefore, for the development of the manufacturing line and the processing steps necessary for the manufacturing of semiconductor devices and the stabilization thereof, it is critical that the failures of the produced semiconductor devices are analyzed, that the causes of failures revealed as a result of such analysis are eliminated and to solve the problems of the manufacturing line and the processing steps which lead up to these problems.
However, since there are several tens of manufacturing devices and hundreds of processing steps involved in the manufacture of one semiconductor device, a big problem is how to quickly find in which manufacturing device or in which processing step the failure occurred. A method of finding the cause of failures has been known in which the detection is done based on the distribution of failures on the wafer of faulty semiconductor devices and the dependency of the failures on the position of wafer in the lot.
More specifically, the manufacturing device or the processing step by which semiconductor devices become faulty can be determined based on the distribution of chips of the faulty semiconductor devices on the wafer and the position of that wafer in the lot.
Japanese Unexamined Patent Application, First Publication, No. Hei 11-45919 (hereinafter referred to as “first related art”) discloses a method in which, when semiconductor substrates (wafers) are manufactured by means of a manufacturing line comprising a plurality of manufacturing devices and desired manufacturing processes (processing steps), such a determination is made based on an inspection step for inspecting the plurality of manufactured semiconductor substrates for the positions of the failures brought about on each semiconductor substrate by means of an inspection device, a failure distribution image data mapping step for designating coordinates of the position data of failures of each semiconductor substrate inspected in the inspection step on an image data composed of pixels arranged on the semiconductor substrate in a grid form and for mapping failure distribution image data on the image data by counting the numbers of failures of the plurality of semiconductor substrates for each of the grid-arranged pixels, and a failure analysis step for comparing the failure distribution image data formed in the failure distribution image data mapping step with a plurality of case databases, from which the cause of failures can be determined, to thereby identify the cause of the failures.
For example, when the distribution of failures on a wafer
100
corresponds to a pattern
111
shown in
FIG. 23
, it can be determined, by comparing the pattern with the case databases produced in the past, that the cause may exist in the step A. When the distribution of failures corresponds to a pattern
113
, it can be determined that the cause may exist in the step C.
In the case of a process wherein one lot of wafers are processed by means of a plurality of manufacturing devices of the same type (manufacturing machine No. A and manufacturing machine No. B) in a single wafer processing, if the number of patterns
115
of the distribution of failures on wafers manufactured by the manufacturing machine No. B is greater than the number of patterns
114
of the distribution of failures on wafers manufactured by the manufacturing machine No. A as shown in
FIG. 24
, it can then be determined that the cause exists in the manufacturing machine No. B.
Although not disclosed in the document of the first related art, a case may happen where faulty semiconductor devices are concentrated in the lower area
102
of each wafer
100
in all the lots of wafers processed at the same time, as shown in FIG.
25
. In such a case, it will be assumed that the cause of failures may exist in an immersion wet etching process where a resist or an oxide film was removed. The reason for this is that when a wafer is immersed in an etchant and then raised, the immersion time of the wafer is longer in the lower portion than in the higher portion, and in addition the etchant flows in the direction of the lower portion when the wafer is raised, so that a pattern or a thin film in the lower portion
102
of the wafer is more deeply etched.
Another case may occur where faulty semiconductor devices are concentrated in the peripheral area of the wafer
100
. In this case, it can be determined that the cause of the failures is a plasma etching device. The reason for this is that the electric field may be uneven in the peripheral area in such a device.
When the number of semiconductor devices which have been judged to be faulty in a wafer numbered W
1
, is significantly high as compared to other wafers numbered W
2
to W
25
in the same lot, it may be assumed that the cause is a batch type processing step. For example, as shown in
FIG. 26
, the wafers numbered W
1
to W
25
are arranged in a direction perpendicular to their main surfaces in a carrier
502
and subjected to a wet etching with a processing liquid
501
in a processing vessel
500
. In this case, each of the wafers numbered W
1
to W
25
is formed with circuits of semiconductor devices on that surface which is indicated by an arrow A. Each of the wafers numbered W
2
to W
25
has a little space on the side of the upper surface, so that the etchant already reacted tends to remain on the surface. In contrast, the wafer numbered W
1
has a lot of fresh etchant on the upper surface as compared to the other wafers, so that the etching process progre
Hara Shin-ichi
Ogawa Sumio
Ueki Minoru
Foley & Lardner
Grant William
NEC Corporation
Rao Sheela S.
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