Semiconductor device manufacturing method, manufacturing...

Details Semiconductor device manufacturing method, manufacturing... Semiconductor device manufacturing method, manufacturing...

1996-12-27

2001-02-06

Gordon, Paul P. (Department: 2786)

Data processing: generic control systems or specific application

Specific application, apparatus or process

Product assembly or manufacturing

C700S096000, C700S110000, C700S117000, C700S119000, C438S062000, C438S486000, C438S490000, C438S676000

Reexamination Certificate

active

06185472

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method, a manufacturing apparatus, a simulation method and a simulator and, more particularly, to a semiconductor device manufacturing method capable of proceeding semiconductor device manufacturing processes according to predetermined schedules or while correcting them by expanding limited quantity or quality contents of “in situ” measured values at their maximum in a sheet type or clustered semiconductor device manufacturing apparatus without using testpieces, a manufacturing apparatus, a simulation method and a simulator.
2. Description of the Prior Art
Conventionally, semiconductor device manufacturing apparatuses have come to the present circumstance after following changes. If such manufacturing apparatus are considered along a series of respective generations, then a chip cost in the DRAM generation and respective generations is varied, as shown in
FIG. 128
, as capacity is increased from a 64K device to a 256 M device. In
FIG. 128
, the ordinate is represented by setting a chip cost in a 1 M device as
1
. In
FIG. 128
, plotted points indicate chip cost and the abscissa denotes DRAM generations.
As shown in
FIG. 128
, from the 64K device to the 256K device, the number of steps is relatively stable and also the chip cost is stable. However, as generations are updated from a 4M device, the number of steps is increased and also the chip cost is increased correspondingly. In order to reduce increase in the cost due to the increase in the number of steps as much as possible, as shown in
FIG. 128
, reduction in cost has been intended by anticipating various countermeasures, e.g., 1) exclusion of waste, 2) standardization of operation, 3) reduction in chip size, 4) promotion of miniaturization, 5) improvement of productivity, 6) promotion of FA, 7) large bore size, etc. in the 64 M device, for instance.
In the 256 M device, by making use of application of new material, introduction of the dielectric substance with high dielectric constant, application of new structure, employment of the solid structure, etc., design has been made along a bi-rule. However, situation is changed completely in the 1G class device and it becomes unclear whether or not design can be made along the bi-rule. According to the conventional approach which pursues high performance of respective manufacturing apparatuses fabricating up to the conventional 256 class device to the limit, it becomes difficult to seek a solution to the enterprise yet. To pursue high performance of respective manufacturing apparatuses to the limit brings about directly high cost.
As shown in
FIG. 129
, high performance apparatus is used for every step in the sequence of steps A-B-C-D-E-F, for example. In this case, it is evident that increase in equipment area and increase in cost are brought: about.
In addition, one more condition to be kept: in mind is that various precise controls due to physical necessity are indispensable in respective steps to more than 1G class device. For example, there are cut-off of contamination, elimination of natural oxide film, pursuit of planarization at atomic level, etc. At present, a clustered manufacturing apparatus as shown in
FIG. 130
, though yet at a study stage, has been proposed as a new concept, with considering these circumstances. The clustered manufacturing apparatus (clustered tool) may be made up as a batch type one, but mainly as a sheet type one. As can be seen from
FIG. 130
, for example, a carrying system is installed in the middle and respective steps are advanced sequentially as shown by an arrow like A-B-C-D. At this time, in many cases the chamber is held at high vacuum at respective steps and in respective steps, so that deposition of natural oxide film can be decreased. In addition, cut-off of contamination and surface control at atomic level are enabled.
In the meanwhile, as for the field effect MIS device formed on the semiconductor, a ferroelectric substance is of necessity directed toward thin film in the course of recent technical development for the high speed and high integration density device. If the ferroelectric substance is formed as a thin film, then a threshold voltage is of course reduced small. As a result, main operation speed is accelerated correspondingly so that especially an AC characteristic can thus be remarkably improved. If EEPROM, etc. are considered, then working condition of the device becomes very severe with the progress of miniaturization. In such case, according to the ferroelectric film formed by the conventional ordinary manufacturing method, sufficient reliability cannot be achieved yet.
However, under such circumstance that, even if the MIS device is miniaturized, characteristic improving measures of the ferroelectric substance per se are not so regarded and as a result power supply voltage is not so reduced, high electric field would be applied to the gate ferroelectric film particularly upon main operation. Still further, electrons and holes generated from the channel region by impact ions are injected into the ferroelectric film according to boundary conditions such as polarity of gate electrodes, drain voltage, etc. These carriers are trapped by the ferroelectric film, so that not only long term reliability is lowered but also reduction in breakdown voltage, eta are caused.
Further, the device will be examined at atomic level. In a thermal ferroelectric film, if high electric field is applied to a silicon ferroelectric film, for example, then Si—O bonds constituting a network interact with high electric field which is applied externally. Then, the bonds are cut off and then trapping centers to trap electrons and holes are formed. Then, electrons and holes being passed subsequently are trapped by the trapping centers. Then, intensity distribution of electric field in the film thickness direction is increased locally rather than an average electric field. In the end, dielectric breakdown is brought out. In recent years, ideas to form the ferroelectric film as single crystal, although still yet at an academic society level, are begun to be proposed to improve such circumstance. For purposes of example, it has been reported in J. Appl. Phys., Vol.69(12), p.8313 (1991) that cerium oxide (CeO
2
) is grown as a single crystal on a silicon (111) face. Otherwise, it has been reported in Japan, J. Appl. Phys. Suppl., Vol.21-1, p.187 (1982) that calcium fluoride (CaF
2
) is grown as a single crystal on the silicon single crystal. These are merely several examples.
In addition, they still remain only in an idea stage and there are some doubts about calculation methods providing the base of guide. In the case that the ferroelectric film is taken as one example, a single crystal per se of the ferroelectric film is not sufficiently recognized. A report concerning the structure of this single crystal ferroelectric film will be checked. There is A. Miyamoto, K. Takeichi, T. Hattori, M. Kubo, and T. Inui, “Mechanism of Layer-Layer Homoopitaxial Growth of SrTiO~(100) as Investigated by Molecular Dynamics and Computer Graphics”, Jpn. J. Appl. Phys. Vol.31, (1992) 4463-4464. In this paper, when a perovskite as a single crystal ferroelectric film is adhered to an underlying Si substrate, a stable structure is calculated. However, initial alignment of angle and distance between Si—O—Ti or Ti—Si—Sr is used incorrectly. Since the structure of the single crystal ferromagnetic film is simplified in these papers, the guide is not always correct.
As understood from the above, it is the existent status that how to design the single crystal ferromagnetic film is scarcely correctly discussed. On the contrary, as for the ferromagnetic film itself, improvement of the characteristic yet remains in refinement of the forming process. For example, preparation of as clean surface as possible previously sputter temperature and sputter atmosphere to form the film, and the like are discussed all the time. We cannot but say that recognition a

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