Semiconductor device manufacturing method by carrying out logic

Semiconductor device manufacturing: process – Including control responsive to sensed condition – Interconnecting plural devices on semiconductor substrate

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438129, 438599, H01L 2100

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active

059131012

ABSTRACT:
In order to modify a combination of logic gates based on relationships between physical locations of the logic gates in a semiconductor integrated circuit which has already been subjected to layout design in the middle of design of the semiconductor integrated circuit, circuit portions whose combination is to be modified are specified, then the circuit portions are transformed into logically equivalent intermediate representations (NAND2s, IVs, etc.), then anew combination of the logic gates is generated based on the intermediate representation, and then the prior combination of the logic gates is replaced with the new combination of the logic gates.

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patent: 5139963 (1992-08-01), Suzuki et al.
patent: 5278105 (1994-01-01), Eden et al.
patent: 5397749 (1995-03-01), Igarashi
Keutzer, "Dagon: Technology Binding and Local Optimization by DAG Matching", 24th ACM/IEEE Design Automation Conference, pp. 341-347, (1987).
Pedram et al., "Layout Driven Technology Mapping", 28th ACM/IEEE Design Automation Conference, pp. 99-105, (1991).
"Layout Driven Logic Synthesis", pp. 17-19, (1992).

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