Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-07-15
2004-02-03
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S710000, C438S712000, C438S720000, C216S047000, C216S059000
Reexamination Certificate
active
06686287
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device and an apparatus for manufacturing the same and, more specifically, to a semiconductor device manufacturing method and apparatus using vapor-phase chemical dry etching.
In recent years, liquid crystal display devices have been extensively used in various fields because of their features of lightweight, flatness, and low power consumption. In particular, active matrix type liquid crystal display devices that are provided with a switching element, such as a thin film transistor (hereinafter referred to as TFT), for each display pixel have been in wide use because they can provide good display image with no crosstalk between adjacent display pixels.
In addition, an attempt has recently been made to form integrally driver circuits onto one of substrates that make up a liquid crystal display panel for the purpose of reducing the number of connections to external circuitry and realizing even higher-definition and thinner display devices.
Some problems are involved in the realization of such a high-definition liquid crystal display device. For example, in the process of manufacturing the array substrate for a liquid crystal display device, various films, which are large in comparison with silicon wafers, must be subjected to fine and uniform patterning over the entire surface.
As a patterning process, there has known a reactive ion etching (RIE) and a vapor-phase chemical dry etching (CDE). In an RIE, a high frequency voltage of, e.g., 13.56 MHz is applied to a substrate to be processed so that an ion is continuously drawn to the substrate based on a self-bias generated at the substrate. In a CDE, a low frequency voltage of, e.g., 6 MHz is applied to a substrate to be processed so that an ion is intermittently drawn to the substrate. In this case, a self-bias of the substrate is substantially zero.
For patterning by dry etching such as RIE or CDE, in order to achieve fine patterning with precise control in each area of the surface, it is important to set accurately the point of time at which the etching terminates, or the end point of etching.
As concerns the end point setting of the etching, various techniques have been proposed hitherto.
For example, in Japanese Unexamined Patent Publication No. 7-70579 or No. 7-66937, there is disclosed an end point determining technique of RIE process that separates variations in process conditions, such as RF power, for obtaining accurate computational results by using a differentiating value based on (electromagnetic radiation intensity at a specific wavelength)/(total electromagnetic radiation intensity). In addition, in Japanese Unexamined Patent Publication No. 9-129597, there is disclosed a technique for improving the accuracy of the end point detection by storing a signal detected when a detection condition is determined as a reference signal, making a comparison between the reference signal and a detected signal for the luminescence intensity at a specific wavelength involved in etching, and determining a signal amplification factor on the basis of the comparison result.
However, no good techniques have been proposed for detecting the end point in performing the CDE process over a large area as in the manufacturing process of liquid crystal display devices. For this reason, with the conventional techniques it is difficult to define fine patterns with precision without variations.
In the manufacturing process of liquid crystal display devices, a metal film or silicon film is patterned by being etched through a resist pattern and, after the termination of etching, a so-called ashing process is performed to remove the resist pattern.
The etching and the ashing process are each performed on a different material, which involves the use of separate processing apparatuses. However, the use of separate processing apparatuses for etching and ashing is time-consuming, lowering manufacturing efficiency, and increasing manufacturing cost.
BRIEF SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor device manufacturing method and apparatus which allows high-accuracy patterning over a large area using CDE and the manufacture of semiconductor devices having good characteristics.
Another object of the present invention is to provide a semiconductor device manufacturing method and apparatus which allows etching and ashing processes to be performed in the same apparatus and the end point of each process to be detected accurately.
Still another object of the present invention is to provide a semiconductor device manufacturing method and apparatus which allows different materials to be etched and the end point of the etching of each material to be detected accurately.
According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: forming a thin film containing silicon over an insulating substrate; forming a resist pattern on the thin film; and patterning the thin film by means of vapor-phase chemical etching using the resist pattern as a mask, the patterning step including a step of detecting, during the vapor-phase chemical etching, a luminescence intensity A of wavelengths within a predetermined wavelength range and a luminescence intensity B at specific wavelengths included in the predetermined wavelength range, a step of dividing the luminescence intensity B by the luminescence intensity A to produce a divide signal, and a step of determining the time of termination of the patterning on the basis of the divide signal.
This manufacturing method allows the end point of vapor-phase chemical etching to be detected with accuracy, allowing for the manufacture of a high-definition and high-performance semiconductor device.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: forming a silicon-containing thin film over an insulating substrate; forming a resist pattern on the thin film; and patterning the thin film by means of vapor-phase chemical etching using the resist pattern as a mask; and after the termination of the patterning, ashing the resist pattern to remove it, the patterning step including a step of detecting a luminescence intensity at a specific wavelength during the patterning and a step of determining the time of termination of the patterning on the basis of a change in the luminescence intensity, and the ashing step including a step of detecting the luminescence intensity at the specific wavelength during the ashing and a step of determining the time of termination of the ashing on the basis of a change in the luminescence intensity.
In the above manufacturing method, each of the patterning and ashing steps includes a step of detecting the luminescence intensity A of wavelengths within a predetermined wavelength range and the luminescence intensity B at specific wavelengths included in the predetermined wavelength range, a step of dividing the luminescence intensity B by the luminescence intensity A to produce a divide signal, and a step of determining the time of termination of the patterning or ashing step on the basis of a change of the divide signal.
The manufacturing method thus arranged allows the common apparatus to be used to detect the time of termination of the patterning and ashing on the basis of the common specific wavelength, resulting in the reduced manufacturing time and cost.
According to still another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: forming a first thin film containing silicon over an insulating substrate; forming a first resist pattern on the first thin film; and patterning the first thin film by means of vapor-phase chemical etching using the first resist pattern as a mask; forming a second thin film containing silicon on the patterned first thin film; forming a second resist pattern on the second thin film;
Kabushiki Kaisha Toshiba
Norton Nadine G.
Pillsbury & Winthrop LLP
Vinh Lan
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