Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Patent
1999-08-20
2000-11-28
Thomas, Tom
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
438113, 438462, 438465, 257786, 257737, 257738, 257778, 257784, H01L 2144, H01L 2148, H01L 2150
Patent
active
06153448&
ABSTRACT:
There is provided a semiconductor device having a chip-size package structure comprising a semiconductor pellet including semiconductor elements, wires, a plurality of electrode pads, and final protection film, an insulation layer serving also as a sealing layer formed to cover the entire surface of the semiconductor pellet having a via hole portion above each of the electrode pads in association therewith, a plurality of wiring patterns formed with a via hole wiring portion electrically connected to the electrode pad at the bottom of each of the via hole portions of the insulation layer and formed with a land portion connected thereto and located in a position offset from the via hole portion, and an external electrode in the form of a ball provided on the land portion of each of the wiring patterns. This makes it possible to provide a semiconductor device in a chip-size package structure in which the length of wires led out from electrode pads is shortened as much as possible to lead out wires from electrode pads near the center of the pellet easily and to allow a pellet having an increased number of external electrodes to be accommodated.
REFERENCES:
patent: 5046161 (1991-09-01), Takada
patent: 5606198 (1997-02-01), Ono et al.
patent: 5677576 (1997-10-01), Akagawa
patent: 5682061 (1997-10-01), Khandros et al.
patent: 5943591 (1999-09-01), Vokoun et al.
Anderson et al., Extended Pad for Testing Package Parts, IBM Technical Disclosure Bulletin, vol. 27 No. 7B, pp. 4210-4211, Dec. 1984.
Katsumata Akio
Takahashi Takuya
Kabushiki Kaisha Toshiba
Parekh Nitin
Thomas Tom
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