Semiconductor device manufacturing method

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

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C438S455000, C438S459000, C257S073000, C257S737000

Reexamination Certificate

active

08048763

ABSTRACT:
A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation potion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion.

REFERENCES:
patent: 6916725 (2005-07-01), Yamaguchi
patent: 7199050 (2007-04-01), Hiatt
patent: 7291911 (2007-11-01), Usami
patent: 7626257 (2009-12-01), Knorr
patent: 7786573 (2010-08-01), Choi et al.
patent: 7795137 (2010-09-01), Saito et al.
patent: 2007/0045836 (2007-03-01), Kwon et al.
patent: 11261000 (1999-09-01), None
patent: 2003151978 (2003-05-01), None
patent: 2004228392 (2004-08-01), None
patent: 2005072489 (2005-03-01), None
patent: 2005222994 (2008-08-01), None
International Search Report for PCT/JP2006/317283 filed Aug. 25, 2006 dated Nov. 21, 2006.
Written Opinion of the International Searching Authority dated Nov. 21, 2006 for International Application No. PCT/JP2006/317283 filed Aug. 25, 2006.
Office Action issued from the Japan Patent Office in corresponding Japanese Patent Application No. 2005-245564 dated Jul. 12, 2011.

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