Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Mesa formation
Reexamination Certificate
2009-07-09
2010-10-19
Mulpuri, Savitri (Department: 2812)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Mesa formation
C438S046000, C438S689000, C438S696000, C438S717000, C438S736000, C438S738000, C438S739000, C438S740000, C438S741000, C257SE21387, C257SE21532
Reexamination Certificate
active
07816162
ABSTRACT:
After a p-type cladding layer, an etching rate reducing layer and a p-type contact layer are formed in order on an n-type substrate, an etching mask is formed. Then, by using the etching mask, the p-type contact layer, the etching rate reducing layer and the p-type cladding layer are partially etched in the region outside the etching mask with an etchant. At this time, the etching rate of the layers by the etchant is slower in the etching rate reducing layer than in the p-type cladding layer and the p-type contact layer. Then, a metal thin film is formed such that the film continuously coats an upper surface and side surfaces of a ridge consisting of the above layers left after the etching step. A normal vector at a surface coated with the thin film has an upward component.
REFERENCES:
patent: 5539239 (1996-07-01), Kawazu et al.
patent: 2005/0152419 (2005-07-01), Kishimoto et al.
patent: 2005/0213628 (2005-09-01), Kishimoto et al.
patent: 2005/0271108 (2005-12-01), Wada et al.
patent: 04111375 (1992-04-01), None
patent: 2000-114660 (2000-04-01), None
patent: 2003-100767 (2003-04-01), None
patent: 2003-163414 (2003-06-01), None
patent: 2004-22833 (2004-01-01), None
USPTO Office Action issued on U.S. Appl. No. 11/357,941, dated Jul. 6, 2007.
USPTO Office Action issued on U.S. Appl. No. 11/357,941, dated Oct. 17, 2007.
USPTO Office Action issued on U.S. Appl. No. 11/357,941, dated Jan. 17, 2008.
USPTO Office Action issued on U.S. Appl. No. 11/357,941, dated Jul. 3, 2008.
USPTO Office Action issued on U.S. Appl. No. 11/357,941, dated Oct. 24, 2008.
USPTO Office Action issued on U.S. Appl. No. 11/357,941, dated Nov. 5, 2008.
USPTO Office Action issued on U.S. Appl. No. 11/357,941, dated Dec. 1, 2008.
USPTO Office Action issued on U.S. Appl. No. 11/357,941, dated Mar. 6, 2009.
Hirukawa Shuichi
Kishimoto Katsuhiko
Ahmadi Mohsen
Birch & Stewart Kolasch & Birch, LLP
Mulpuri Savitri
Sharp Kabushiki Kaisha
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