Semiconductor device manufacturing method

Details Semiconductor device manufacturing method Semiconductor device manufacturing method

2002-10-15

2004-04-20

Ho, Hoai (Department: 2818)

Semiconductor device manufacturing: process

Including control responsive to sensed condition

Optical characteristic sensed

Reexamination Certificate

active

06723571

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device manufacturing method, and more specifically relates to the semiconductor device manufacturing method having a pretreatment to prevent an etching rate from varying.
2. Description of the Related Art
As semiconductor devices become more integrated, their patterns are required to be more precise. A highly precise and stable dry etching technique is desired for fulfilling such requirements.
Referring to
FIGS. 4A and 4B
, a conventional etching process will be explained. This conventional etching process shown in
FIGS. 4A and 4B
is a process for etching an insulator between layers using an ICP etching apparatus.
Referring to
FIG. 4A
, after the ICP etching apparatus is cleaned, a dummy wafer is used for running.
An etching reactive chamber
41
of the ICP apparatus has a quartz board
42
supporting a planar coil
43
, and a quartz window
44
as a monitoring port. Contained inside of the etching reactive chamber
41
is a stage
45
serving as an electrode on which a work piece is mounted. The etching reactive chamber
41
is grounded, and high frequency power for plasma excitation is applied to the planar coil
43
from an exciting RF power supply
47
. On the other hand, bias power is applied to the stage
45
from a bias RF power supply
46
.
In the running operation, a dummy wafer
48
having a polyimide layer
49
is used. The polyimide layer
49
is the same as the insulator formed on a semiconductor wafer to be etched. A gas is introduced to the etching reactive chamber
41
, and is converted to plasma by the exciting RF power to etch the polyimide layer
49
.
Referring to
FIG. 4B
, after the dummy wafer
48
is removed, a semiconductor wafer to be etched is mounted on the stage
45
. The polyimide layer
59
, the insulator between layers, is selectively etched to open a contact hall
61
.
The semiconductor wafer in this conventional example is prepared by the following process:
On a semi-insulating GaAs substrate (not shown), via an i-type AlGaAs buffer layer (not shown), an i-type InGaAs electron transit layer (not shown) is epitaxially grown. On the i-type InGaAs electron transit layer, an n-type AlGaAs electron supplying layer
51
and an n-type GaAs cap layer
52
are sequentially epitaxially grown. Source and drain electrodes
53
each comprising an AuGe layer
54
and an Au layer
55
are formed on the n-type GaAs cap layer
52
. After a gate recess region is formed, a T-type gate electrode
56
comprising a Pt layer
57
and an Au layer
58
is formed. Then a polyimide layer
59
as an interlaminar insulator is provided to obtain the desired semiconductor wafer.
In the etching operation, a resist pattern
60
with an opening on the polyimide layer
59
is used as a mask. The opening of the resist pattern
60
desirably corresponds to the contact hall
61
of the polyimide layer
59
. O
2
gas is introduced to the etching reactive chamber
41
, and plasma is generated. The generated plasma selectively etches the polyimide layer
59
to open to the contact halls
61
(one is shown) each reaching one of the source or drain electrodes
53
.
Subsequently, a TiW layer as a barrier metal and an Au layer as a plating base layer are formed by sputtering. Then an Au wiring layer is formed by a selective plating technique using a plating frame having a resist pattern, which is not explained in detail.
In this etching apparatus, however, repetition of the process of etching the interlaminar insulator layer causes drastic change in etching rate at the beginning of the etching process and makes the etching process unstable. This problem will be explained below with reference to
FIGS. 5A and 5B
.
FIG. 5A
is an experimental graph showing etching rates depending on the number of repetitions of the etching process as shown in FIG.
4
B. It was observed that the etching rate steeply decreases at the beginning of the etching repetition and then becomes stable. In this experiment, the etching was performed for one minute at one time. It is shown in the graph that the etching rate goes down to about a half at the tenth time of etching.
FIG. 5B
is a similar graph showing etching rates depending on the number of repetitions of the etching process, in which the Au layers
55
of the source and drain electrodes are not exposed for comparison purposes. It is shown that the etching rate does not change so much.
In comparing
FIGS. 5A and 5B
, it is believed that the steep change in the etching rate at the beginning of the etching process is due to the exposure of the Au layer
55
. More specifically, in the process of opening the contact hall
61
, the Au layer
55
is exposed and a portion of the Au flies (becomes airborne) and is scattered in the etching reactive chamber
41
, which is believed to be the cause of the etching rate decrease. This etching rate decrease is found also in the case that the exposed metal is Pt, Cu, or Al.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device manufacturing method that substantially prevents the etching rate variation so as to provide excellent reproducible etching results.
Features and advantages of the present invention will be set forth in the description that follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by the semiconductor device manufacturing method particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
In order to attain the object, the semiconductor device manufacturing method of the present invention includes a plasma etching process performed on a surface of the semiconductor device, and the semiconductor device has a specific metal therein that is unexposed at the surface at the beginning stage of the etching process; the specific metal gets exposed during the etching process; the existence of the specific metal in an etching reactive chamber affects the etching rate of the semiconductor device; and the method is characterized in that the specific metal is plasma etched as pretreatment before starting the plasma etching process of the semiconductor device.
In this manner, the specific metal is sputtered in the etching reactive chamber by plasma etching to stabilize the etching rate. In the present specification and claims, the term “plasma etching” includes ion milling performed by making plasma of a gas such as Ar.
According to another feature of the present invention, in the semiconductor device manufacturing method as described above, the pretreatment comprises a step of plasma etching the specific metal disposed on a dummy substrate.
In this manner, the specific metal can be sputtered in the etching reactive chamber by using a dummy substrate during the conventional running operation. Therefore, the etching rate can be stabilized without increasing manufacturing processes of the semiconductor device.
According to another feature of the present invention, a semiconductor device manufacturing method includes a plasma etching process performed on a surface of the semiconductor device, the semiconductor device having a first specific metal therein that is unexposed at the surface at the beginning stage of the etching process; the first specific metal gets exposed during the etching process; the existence of the first specific metal in an etching reactive chamber affects the etching rate of the semiconductor device; and the method comprises a step of introducing a gas containing a second specific metal into the etching reactive chamber as pretreatment before starting the plasma etching process of the semiconductor device.
In this manner, the first specific metal can be sputtered in the etching reactive c

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