Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2001-07-06
2004-05-18
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
C438S118000
Reexamination Certificate
active
06737285
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and relates in particular to a method for manufacturing a semiconductor device whereby a smaller mounting area can be provided by reducing the external size of a package without using lead forming, and a considerable reduction in manufacturing costs can be realized.
In a process for the manufacture of semiconductor devices, multiple semiconductor chips, produced from a single wafer by dicing, are securely mounted in a lead frame, after which transfer molding, using a die and resin injection, is used to seal them. The thus sealed semiconductor chips are then separated to provide multiple individual semiconductor devices. For this process, either a strip-shaped or a hoop-shaped lead frame is employed, but regardless of which type of lead frame is used, only a single sealing procedure is required to simultaneously seal a plurality of semiconductor devices.
FIG. 12
is a diagram showing a transfer molding process. During this process, the semiconductor chip
1
fixed to a die pad of a lead frame
2
by die bonding or wire bonding is mounted inside a cavity
4
, formed of an upper and a lower die
3
A and
3
B, and an epoxy resin is injected into the cavity
4
to seal the semiconductor chip
1
. Once the process has been completed, the lead frame
2
is cut to complete the fabrication of a separate semiconductor device (e.g., Japanese Patent Publication No. H05-129473).
For this process, as is shown in
FIG. 13
, multiple cavities
4
a
to
4
f
, a resin source
5
for injecting a resin, a runner
6
, and gates
7
for injecting the resin into the cavities
4
a
to
4
f
via the runner
6
, are formed in the surface of the die
3
B. For example, if ten semiconductor chips
1
are mounted on a single lead frame, ten cavities
4
, ten gates
7
and one runner
6
are formed for one lead frame. And the cavities
4
equivalent to, for example, twenty lead frames are formed in the inner surfaces of the die
3
.
FIG. 14
is a diagram showing a semiconductor device obtained by transfer molding. The semiconductor chip
1
whereon elements, such as transistors, are formed is securely attached to an island
8
of the lead frame by a brazing material
9
, such as solder; the electrode pad of the semiconductor chip
1
is connected to a lead terminal
10
by a wire
11
; the periphery of the semiconductor chip
1
is covered with a resin
12
that conforms to the shapes of the cavities
4
; and the distal end of the lead terminal
10
is extended outside the resin
12
.
Since, in a conventional package, the lead terminal
10
for an external connection is exposed, outside the resin
12
, the distance up to the tip end of the lead terminal
10
must be considered as being part of the mounting area, and thus, the mounting area is much larger than the external dimensions of the resin
12
.
Further, since according to the conventional transfer molding technique the resin is hardened under pressure, even the resin in the runner
6
and the gates
7
is hardened, and the residual resin therein must be disposed of. Thus, according to the method using the above lead frame whereby the gates
7
are provided for the individual semiconductor devices that are to be manufactured, efficiency in the use of the resin is low, and relative to the amount of resin employed, only a small number of semiconductor devices can be manufactured.
Further, since, after a transfer molding process a lead frame is separated into tiny packages comprising individual semiconductor devices, it is extremely difficult to handle the obtained semiconductor devices when they must be measured or stored in tape because it is difficult to determine which are their obverse and which are their reverse sides, and because of how the lead terminals are positioned. As a result, work efficiency is adversely affected and greatly deteriorated.
SUMMARY OF THE INVENTION
To achieve the shortcomings, according to the invention, a method for manufacturing a semiconductor device comprises the steps of:
bonding one semiconductor chip to each of multiple mounting portions of a substrate;
covering the semiconductor chips bonded to the mounting portions with a common resin layer;
bringing the substrate into contact with the resin layer and gluing the substrate to a adhesive sheet;
performing dicing and measurement for the semiconductor chips that are glued to the adhesive sheet. Thus, the semiconductor chips that are integrally supported by the adhesive sheet can be measured, without the having to be separated into individual semiconductor devices.
Further, according to the invention, a method for manufacturing a semiconductor device comprises the steps of:
bonding a semiconductor chip to each of multiple mounting portions of a substrate;
covering the semiconductor chips bonded to the mounting portions with a common resin layer;
bringing the substrate into contact with the resin layer and gluing the substrate to an adhesive sheet;
dicing and measuring the semiconductor chips while the substrate is glued to the adhesive sheet; and
storing directly in a carrier tape semiconductor devices glued to the adhesive sheet. Thus, the semiconductor chips can be processed while integrally supported by the adhesive sheet, and need not be separated into individual semiconductor devices until they are stored in a carrier tape.
REFERENCES:
patent: 5814894 (1998-09-01), Igarashi et al.
patent: 5896036 (1999-04-01), Wood et al.
patent: 6048750 (2000-04-01), Hembree
patent: 6080602 (2000-06-01), Tani et al.
patent: 6113728 (2000-09-01), Tsukagoshi et al.
patent: 6211960 (2001-04-01), Hembree
patent: 6215194 (2001-04-01), Nakabayashi
patent: 6309911 (2001-10-01), Hyoudo et al.
patent: 6368893 (2002-04-01), Tani et al.
patent: 6495379 (2002-12-01), Iketani
patent: 6528330 (2003-03-01), Iketani
patent: H05-129473 (1993-05-01), None
Hyodo Haruo
Iketani Koji
Shibuya Takao
Tani Takayuki
Fish & Richardson P.C.
Fourson George
Sanyo Electric Co,. Ltd.
Toledo Fernando
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