Semiconductor device manufacturing method

Details Semiconductor device manufacturing method Semiconductor device manufacturing method

1999-09-15

2002-11-12

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

With measuring or testing

C438S015000, 43, 37

Reexamination Certificate

active

06479305

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device manufacturing method including an inspection step for inspecting the circuit elements of manufactured semiconductor devices and, more particularly, to a semiconductor device manufacturing method or a semiconductor device inspecting method which is suited to make the inspection step simple and efficient and to a jig for use in such methods.
First of all, a conventional semiconductor device manufacturing method will be described below with reference to
FIGS. 13 and 14
attached hereto.
FIG. 13
is a flowchart schematically showing a representative semiconductor device manufacturing method, particularly, the portion of a manufacturing process including an inspection step according to the present invention. FIGS.
14
(
a
) to
14
(
c
) show various forms of semiconductor devices manufactured in various steps of the semiconductor device manufacturing process.
Conventionally, semiconductor devices are generally manufactured by a manufacturing method including the following major steps. The sequence of the steps coincides with the sequence described below.
(1) Previous Step
The previous step is the step of forming a multiplicity of LSI (large-scale integrated circuit) chips
1
b
formed by integrating a multiplicity of circuit elements over a semiconductor wafer
1
a.
(2) Probing Inspection Step
The probing inspection step is the step of carrying out so-called initial screening of the multiplicity of LSIs formed over the semiconductor wafer
1
a
in the above-described step (1) by using probes on a chip-by-chip basis, to determine whether each of the LSIs is defective or nondefective.
(3) Cutting Step
The semiconductor wafer
1
a
over which the LSIs are formed in the above-described step (1) is normally cut and separated into the individual chips
1
b
by using, for example, a laser beam or a dicer.
(4) Mounting or Packaging Step
The mounting or packaging step is the step of mounting each of the chips
1
b
obtained in the above-described step (3on a so-called socket
2
or causing each chip-shaped electrode pad to independently conduct to a leadframe so that the chips
1
b
can be adapted to the subsequent steps (inspection steps), and then packaging them with resin or the like, thereby forming objects to be inspected in the subsequent inspection steps.
(5) Burn-in Step
The burn-in step is the step of imparting electrical or thermal stress to a plurality of objects to be inspected, which have been obtained in the above-described step (4), at the same time for a long period of time, thereby accelerating and screening out potential defects in the manufactured LSI chips
1
b.
(6) Screening Inspection Step
The screening inspection step is the final inspection step which are performed on the reliability of semiconductor devices after the above-described steps (1) to (5).
In each of the above-described probing inspection, burn-in and screening inspection steps, probes which are disposed to positionally and dimensionally correspond to predetermined electrode pads
1
c
formed on the semiconductor wafer
1
a
or the chips
1
b
are brought into contact with the electrode pads
1
c,
and each of the electrode pads
1
c
is made to independently conduct to an inspection system which is not shown, thereby carrying out a predetermined inspection.
However, as is also apparent from the above description, the above-described initial probing inspection step is performed with the semiconductor wafer
1
a
over which the multiplicity of LSI chips
1
b
are formed, as shown in FIG.
14
(
a
). On the other hand, in the subsequent inspection steps including the burn-in step, it is common practice that these steps are performed with the LSI chips
1
b
obtained by cutting the LSIs of the semiconductor wafer
1
a
into chips, as shown in FIG.
14
(
b
).
More specifically, during each of the inspection steps executed after the LSI chips
1
b
are cut out from the semiconductor wafer
1
a,
the respective LSI chips
1
b
are individually mounted on the sockets
2
, as shown in FIG.
14
(
c
), and the sockets
2
are individually mounted via pins
2
a
on a board (not shown) which conforms to the specifications of an inspection step being executed, and then the board on which the LSI chips are installed is mounted in an inspection system, whereby a predetermined electrical connection is provided and a predetermined inspection is carried out.
Incidentally, an example in which, unlike the above-described steps, the plurality of chips
1
b
separated by cutting are directly mounted on an inspection board without using the above-described type of socket
2
is described in, for example, Japanese Patent Laid-Open No. 131048/1991. Another example in which a wafer itself is subjected to burn-in without being cut into chips is described in, for example, Japanese Patent Laid-Open No. 204621/1988.
SUMMARY OF THE INVENTION
However, the above-described prior art has the following problems.
First, in the semiconductor device manufacturing method according to the prior art described above with reference to
FIGS. 13 and 14
, the respective chips
1
b
cut out from the semiconductor wafer
1
a
need to be mounted on the sockets
2
, i.e., one chip to be inspected needs to be mounted on one socket.
For this reason, the number of time-consuming steps for mounting and removing separate chips to be inspected in and from sockets increases, and if electrical conduction is to be provided between the chips to be inspected and the sockets, predetermined operations and costs will occur. If the inspection costs of semiconductor devices are to be reduced by preventing the operations and costs for such electrical conduction from being caused by initial defective chips, it is necessary to carry out a probing inspection before the chips to be inspected are mounted in the sockets, as shown in the flowchart of
FIG. 13
, thereby eliminating the initial defective chips before the cutting step. However, this results in the problem that the number of inspection steps increases and inspection costs also increase.
In addition, as described in the above-cited Japanese Patent Laid-Open No. 131048/1991 as well, if an inspection is to be carried out with chips to be inspected being directly mounted on the inspection board, it is necessary to prepare a microprobe group in which a plurality of probes are disposed on the board itself in an arrangement corresponding to the arrangement of fine electrode pads on the surfaces of small chips to be inspected. However, the production of such microprobe group is expensive, and if chips to be inspected are various in kind (shape or dimension), a multiplicity of expensive microprobe groups need to be prepared for such various kinds of chips. This will lead to great equipment costs and hence increases in inspection costs.
Furthermore, as is known from the above-cited Japanese Patent Laid-Open No. 204621/1988, in the method of subjecting manufactured LSI chips to burn-in in the wafer state thereof, the number of electrodes to collectively electrically conduct to an inspection system is huge because recent large-diameter wafers have a multiplicity of LSIs. For this reason, the microprobe group required to connect the LSI chips to an inspection board to carry out burn-in in the wafer state is difficult to realize, and even if such a microprobe group is realized, the microprobe group becomes very expensive and requires huge equipment costs, and inspection costs likewise increase. In addition, if a huge number of electrodes are connected, the number of the electrodes may exceed the processing capability of the inspection system. Furthermore, there is the problem that the amount of deviation of the relative position between the probes and the electrode pads on a wafer due to thermal expansion increases in the outer circumferential portion of the wafer, so that both the probes and the electrode pads may become unable to physically contact each other.
Therefore, in view of the problems of the above-described prior art, the object o

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