Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Including isolation structure
Reexamination Certificate
1999-05-21
2002-01-08
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Including isolation structure
C438S377000, C438S376000
Reexamination Certificate
active
06337252
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a technical field of semiconductor devices, and particularly to a method of manufacturing a semiconductor device in which a vertical (vertical type) PNP bipolar transistor (hereinafter referred to as “V-PNP”) or a vertical (vertical type) NPN bipolar transistor (hereinafter referred to as “V-NPN”) is formed on a semiconductor substrate.
2. Description of the Related Art
There have been hitherto utilized various methods of manufacturing semiconductor devices having V-PNP disclosed in Japanese Patent Application Laid-open No. Hei-9-223746, Japanese Patent Application Laid-open No. Hei-9-307011, etc.
According to a first conventional method, a high-concentration N-type impurities region
42
is formed in a partial area of a P-type silicon substrate
1
, and then a high-concentration P-type impurities region
43
is formed on the high-concentration N-type impurities region
42
as shown in FIG.
16
. Thereafter, an epitaxial layer
44
containing N-type impurities is grown on the overall surface of the substrate.
Subsequently, as shown in
FIG. 17
, a field oxide film
2
is selectively formed by LOCOS method to fix a transistor region, and then the substrate surface is oxidized to form an oxide film having a thickness of 20 to 30 nm. Thereafter, P-type impurities are doped from the substrate surface by an ion implantation method using a photoresist (not shown) as a mask, and then a heat treatment is carried out to form a collector drawing region
45
. Thereafter, a P-type collector region
46
having a low impurity concentration is formed on the high-concentration P-type impurity region
43
.
Subsequently, as shown in
FIG. 18
, an N-type intrinsic base region
10
and an external base region
20
are formed, and then an emitter contact
12
is formed in an oxide film
11
which is grown on the overall surface.
Subsequently, as shown in
FIG. 19
, boron is doped into a polycrystalline silicon layer grown on the overall surface, and the polycrystalline silicon layer is subjected to a patterning treatment by using a photoresist as a mask (not shown) to form an emitter electrode
16
. Thereafter, the heat treatment is carried out to diffuse boron from the polycrystalline silicon layer of the emitter electrode
16
to the silicon substrate, thereby forming a P-type emitter region
24
.
Thereafter, as shown in
FIG. 20
, an interlayer insulating film
25
is formed on the overall surface, tungsten is buried into a contact
26
formed in the interlayer insulating film
25
and then an aluminum wiring
28
is formed, thereby forming V-PNP.
In the manufacturing method described above, an N-type buried layer
42
and an N-type epitaxial layer
44
must be formed to separate the P-type collector region
46
from the P-type substrate
1
, and thus the number of manufacturing steps is large. As a method of reducing the number of manufacturing steps has been proposed a manufacturing method shown in
FIGS. 21
to
24
(second conventional method).
According to the second conventional method, as shown in
FIG. 21
, a field oxide film
2
is formed on a P-type silicon substrate
1
, p-type impurities are doped from the substrate surface by ion implantation and then the heat treatment is carried out to diffuse impurities, thereby forming a P-type collector drawing region
45
having a high impurity concentration. Thereafter, an N-type impurity region
47
is formed.
Subsequently, as shown in
FIG. 22
, P-type impurities and N-type impurities are doped into the inside of the N-type impurity region
47
by ion implantation in the same mask step to form a P-type collector region
46
and an N-type base region
10
. The N-type impurity region
47
is provided to separate the P-type collector region
46
and the P-type substrate from each other. Thereafter, an external base region
20
is formed.
Subsequently, as shown in
FIG. 23
, an emitter contact
12
is formed in an oxide film
11
grown on the overall surface, and then boron is ion-implanted into a polycrystalline silicon layer grown on the overall surface. Thereafter, the patterning treatment is carried out to form an emitter electrode
16
. Thereafter, the heat treatment is carried out to diffuse boron from the polycrystalline silicon layer of the emitter electrode
16
to the silicon substrate
1
, thereby forming a P-type emitter region
24
.
Subsequently, as shown in
FIG. 24
, an interlayer insulating film
25
is formed on the overall surface, tungsten is buried into a contact
26
formed in the interlayer insulating film
25
, and then an aluminum wiring
28
is formed, thereby forming V-PNP.
In the above-described second conventional method, the P-type collector region
46
and the N-type impurity region
47
used for element isolation are formed in different mask steps. These steps cannot be commonly used with a step of forming CMOS or vertical type NPN bipolar transistor, and thus when CMOS transistor or V-NPN and V-PNP are formed on the same substrate, the number of manufacturing steps and the number of mask steps are increased.
The above is applied to an inverse conduction type case (that is, P is substituted by N and N is substituted by P).
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a semiconductor device manufacturing method which can form V-PNP or V-NPN with a small number of steps and a small number of masks.
Another object of the present invention is to provide a semiconductor device manufacturing method which can commonly use (i.e., simultaneously carry out) a part of a step of forming V-PNP or V-NPN with a step of forming the other elements when the other elements such as transistors, etc are formed on the same substrate together with V-PNP or V-NPN.
In order to attain the above object, according to a first aspect of the present invention, a method of manufacturing a semiconductor device having a vertical PNP bipolar transistor formed on a P-type semiconductor substrate, is characterized in that a step of forming an N-type bottom separation region on the P-type semiconductor substrate to separate or isolate the vertical PNP bipolar transistor, a step of forming a P-type collector region of the vertical PNP bipolar transistor, and a step of forming an N-type base region of the vertical PNP bipolar transistor are performed by using the same mask.
In the above method, the formation of the N-type bottom separation region, the formation of the P-type collector region and the formation of the N-type base region my be performed by using impurity-ion implantation.
In the above method, prior to the step of forming the N-type bottom separation region, an N-type side separation region may be formed in the P-type semiconductor substrate to separate or isolate the vertical PNP bipolar transistor, and the N-type bottom separation region, the P-type collector region and the N-type base region may be formed within an area which is separated by the N-type side separation region.
In the above method, an N-type side separation region may be formed in the P-type semiconductor substrate to separate or isolate the vertical PNP bipolar transistor after the N-type bottom separation region, the P-type collector region and the N-type base region are formed.
In the above method, the formation of the N-type side separation region may be performed by using impurity-ion implantation.
Further, in order to attain the above object, according to a second aspect of the present invention, a method of manufacturing a semiconductor device having a vertical PNP bipolar transistor and the other element which are formed on a P-type semiconductor substrate, is characterized in that simultaneously with an N-type impurity region forming step when the other element is formed on the P-type semiconductor substrate, N-type impurities are doped into a desired region of the P-type semiconductor substrate to form an N-type side separation region for separation or isolation of the vertical PNP bipolar transistor.
In the above method, the formation
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