Semiconductor device manufacturing method

Details Semiconductor device manufacturing method Semiconductor device manufacturing method

1999-03-10

2001-05-01

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

Reexamination Certificate

active

06225184

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and, more particularly, a semiconductor device manufacturing method including the step of forming contact holes.
2. Description of the Prior Art
A higher integration density of the semiconductor memory device such as DRAM (Dynamic Random Access Memory), FeRAM (Ferroelectric Random Access Memory), etc. has been advanced. In pursuant to such higher integration density, it is driven by necessity to reduce further diameters of the contact holes which are formed in an interlayer insulating film.
For example, a contact hole for connecting a fin-type capacitor and an impurity diffusion layer of the DRAM cell is formed along steps described in the following.
First, as shown in
FIG. 1A
, a first interlayer insulating film
103
is formed on active regions of a semiconductor substrate
101
and a field insulating film
102
which is formed around the active regions. Then, bit lines
104
are formed on the first interlayer insulating film
103
. The bit lines
104
are connected to a part of the impurity diffusion layers formed in the active regions via contact holes (not shown) formed in the first interlayer insulating film
103
respectively.
In addition, a second interlayer insulating film
105
is formed on the bit lines
104
and the first interlayer insulating film
103
, and then a first insulating film (SiN)
106
is formed thereon. Then, a plurality of second insulating films (SiO
2
)
107
and first semiconductor (silicon) films
108
are formed alternatively on the first insulating film
106
. Then, resist
109
is coated on the uppermost second insulating film
107
, and then windows
109
a
are formed in the resist
109
by exposing and developing the resist
109
. The windows
109
a
are formed over capacitor contact regions. The capacitor contact regions are placed over another impurity diffusion films
110
which are formed on the active regions.
Then, as shown in
FIG. 1B
, holes
111
are formed in respective films from the uppermost second insulating film
107
to the first interlayer insulating film
103
by etching such films successively via the windows
109
a
of the resist
109
.
Then, the resist
109
is removed and then, as shown in
FIG. 1C
, a second silicon film
112
is formed in the holes
111
and on the uppermost second insulating film
107
. Then, as shown in
FIG. 1D
, the second silicon film
112
, the first silicon films
108
, and the second insulating films
107
except for lowermost second insulating film
107
formed on the first insulating film
106
are patterned, so that these films are formed to have a planar shape of a storage electrode of the capacitor. Then, all the second insulating films
107
are selectively removed by using an etchant. As a result, as shown in
FIG. 1E
, fin-type storage electrodes
113
consisting of the first silicon films
108
and the second silicon film
112
appear on the semiconductor substrate
101
.
In turn, as shown in
FIG. 1F
, a dielectric film
114
is formed on a surface of the fin-type storage electrodes
113
, and then a silicon film serving as an opposing electrode
115
is formed on a surface of the dielectric film
114
.
In the steps of forming the capacitor of the above DRAM, an i-line is employed in exposure when the windows
109
a
are formed in the resist
109
and a phase shifter is employed as an exposure mask.
However, even if the i-line and the phase shifter are employed in exposure of the resist
109
, a diameter of the window
109
a
in the resist
109
is limited to about 0.31 &mgr;m at a minimum.
In order to reduce the diameter of the window
109
a
further, there is the technology in which an excimer stepper is applied to the exposing step. However, such technology has not been regularly spread yet.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device manufacturing method including the step of forming holes each having an infinitesimal diameter which exceeds the limit or critical value in the existing exposure technology.
According to the present invention, when the a contact hole which is employed to connect electrically the storage electrode constituting the capacitor to the impurity diffusion layer on the semiconductor substrate is formed, the first insulating film, the first semiconductor film, and the second insulating film are formed in sequence on or above a semiconductor substrate, then the resist mask having a window therein is formed on the second insulating film, then a first hole is formed in the second insulating film via the window or the first hole is formed in the second insulating film and the first semiconductor film, then an overetching using a halogen compound gas is performed to form a sidewall on an inner peripheral surface of the first hole, and then a second hole having a small diameter are formed by etching through the first hole surrounded by the sidewall and the resist.
Accordingly, the diameter of the second hole which are placed below the sidewall isreduced smaller than those in the prior art, so that a higher integration density of the capacitor is accomplished.
Moreover, since the diameter of the first hole (i.e., the upper part of the contact hole) is formed larger than the diameter of the second hole (i.e., the lower part of the contact hole), the step coverage of the conductive film which is formed in the contact hole and on the second insulating film is improved.


REFERENCES:
patent: 5705420 (1998-01-01), Ema
patent: 6071812 (2000-06-01), Hsu et al.

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