Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-05-03
2003-04-22
Hjerpe, Richard (Department: 2775)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S207000, C345S087000, C345S088000, C345S089000, C250S210000, C250S210000, C250S210000, C250S227110, C250S227120, C250S227280
Reexamination Certificate
active
06552712
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device, liquid crystal display and electronic equipment including these, and, more particularly, to a semiconductor device which is used in an environment exposed to external light.
BACKGROUND ART
In general, when a semiconductor circuit is irradiated with light, an electric current is generated in the semiconductor circuit causing a malfunction. Therefore, in order to prevent such occurrence of an electric current due to light in a semiconductor circuit, a mounting form for packaging the semiconductor circuit to shade it from light has been basically adopted. Specifically, an IC chip on which a semiconductor circuit has been formed is mounted on a circuit board such as a molded material to be packaged, and a liquid crystal display is formed by connecting the packaged circuit board and an LCD panel substrate by a heat seal. Alternatively, the liquid crystal display is also formed by connecting a TCP (Tape Carrier Package) in which an IC chip is mounted on a tape with a conductive film to the LCD panel substrate.
In such a mounting form (TCP or packaged circuit board), it is possible to shade light with a molded material at a mounted position.
However, in the form of a mounting module referred to as a COG (Chip On Glass) in which an IC chip is mounted on a side of a LCD panel substrate, the IC chip is mounted on a glass substrate constituting the LCD panel substrate, so that the IC chip can not be packaged and also light can not be shaded.
The reason will be described in more detail using, for example, a liquid crystal drive circuit indicated in FIG.
19
. An example of a drive circuit for a COG (Chip On Glass) type of general liquid crystal display is indicated in
FIGS. 19A and 19B
. A semiconductor circuit used in an environment exposed to external light is hereinafter referred to as “a principal circuit”.
In
FIG. 19A
, a liquid crystal LC is enclosed between a transparent glass substrate
1381
and an LCD panel
1382
. A pixel electrode array
1383
(a layer for forming the pixel electrode array) is formed on the glass substrate
1381
. In addition, a principal circuit
1384
which is composed of semiconductor elements such as IC chips is also formed on the glass substrate
1381
. The principal circuit
1384
includes, for example, a shift register circuit, drive circuit, and power supply circuit Hereinafter, a power supply circuit will be used as an example of this principal circuit.
FIG. 19B
shows a partially enlarged portion of the principal circuit shown in FIG.
19
A. The principal circuit
1384
is mounted on the glass substrate
1381
through an anisotropic dielectric film (AFC)
1385
. Incidentally, a terminal pulled out from the principal circuit
1384
is connected to an external circuit through a flexible connector, which is not shown. Furthermore, the principal circuit
1384
is covered with an opaque resin layer
1386
for circuit protection and an aluminum film for a shield, not shown. Therefore, the principal circuit
1384
is not exposed to direct light from the upper side of
FIGS. 19A and 195
.
However, a part of the light passing through the LCD panel
1382
(for example, light from back light and natural light) irradiates the principal circuit
1384
through the inside of the glass substrate
1381
along a path indicated by the arrow F in FIG.
19
A. Thus, carriers based on this light are light excited in addition to a usual drive current in the principal circuit
1384
to generate an unnecessary current (hereinafter, this current is referred to as “a light excited current”).
In order to remove such a disadvantage, it is conceivable to prevent the occurrence of the light excited current described above by shading based on the methods of making the anisotropic conductive film
1385
completely opaque and incorporating pigment in the anisotropic conductive film
1385
.
However, when an alignment mark is formed on the surface of the glass substrate
1381
to mount the principal circuit
1384
formed in an IC chip, the alignment mark will be hidden by the anisotropic conductive film
1385
when the IC chip is bonded to the glass substrate, so that it is impossible to align the principal circuit
1384
and the glass substrate
1381
.
Moreover, even if the alignment can be performed advantageously by making the anisotropic conductive film
1385
opaque, the electric and chemical characteristics of the semiconductor circuit may deteriorate because of the pigment.
In addition, when the anisotropic conductive film
1385
is depressed in the vertical direction, included metal particles are caused to contact each other to make the depressed portion electrically conductive. For this reason, if a thick anisotropic conductive film
1385
is formed in order to improve the shading function, the mutual contact of the metal particles due to depression is not performed advantageously, so that electric conduction can not be assured.
Next, a circuit configuration of the principal circuit
1384
will be explained. In this case, a power supply circuit constituting the principal circuit typically has a bias circuit with outputs of Vout
1
to Vout
5
in multiple stages, for example, five stages in order to drive an LCD panel and LCD drive circuit by using a voltage drop method or MLS. Problems when the light excited current described above is generated in the power supply circuit will be explained below with reference to
FIGS. 20A and 20B
.
FIG. 20A
is a circuit diagram showing a conventional power supply circuit. This power supply circuit is composed of a multistage connection circuit in which n-type FETs
1391
to
1395
are connected in multistage, and a bias voltage VDD is applied to one end and a voltage V
1
is applied to the other. In addition, voltages Vout
0
and Vout
5
are output from both ends of this multistage connection circuit. Each of the voltages vout
1
to Vout
4
is output through voltage follower circuits A
1
to A
4
from between a source electrode of FET
1391
and a drain electrode of FET
1392
, between a source electrode of FET
1392
and a drain electrode of FET
1393
, between a source electrode of FET
1393
and a drain electrode of FET
1394
, and between a source electrode of FET
1394
and a drain electrode of FET
1395
, respectively.
FIG. 20B
is a cross-sectional view of the structure of a portion of the FETs
1391
and
1392
in the power supply circuit. The FETs
1391
and
1392
are formed on an n-type substrate
1401
. P-type well regions
1402
are formed in the n-type substrate
1401
, and n-type drain regions
1403
and n-type source regions
1404
are formed in the p-type well regions
1402
. Additionally, gate electrodes
1405
are formed above and between the n-type drain regions
1403
and n-type source regions
1404
through an insulation layer not shown. A voltage VDD is applied to the gate electrode
1405
of the FET
1391
, n-type drain regions
1403
, and the n-type substrate
1401
. The VDD is also connected to an output terminal Vout
0
, and the n-type source region
1404
of the FET
1391
and the n-type drain region
1403
of the FET
1392
are connected to an output terminal Vout
1
.
The connections between the FETs
1392
and
1393
, FETs
1393
and
1394
, and FETs
1394
and
1395
are similar to that between the FETs
1391
and
1392
, so that the n-type source electrodes of the FETS in the front stages are connected to the n-type drain regions and gate electrodes of the FETS in the later stages. Further, the connection lines for each FET are connected to output terminals Vout
2
to Vout
4
through the voltage followers A
2
, A
3
, and A
4
, respectively.
FIG. 20B
shows that external light having an energy of h&ngr; irradiates the back side of the n-type substrate
1401
, where h is Planck's constant and &ngr; is c/&lgr; (c is the velocity of light and &lgr; is the wavelength). When this external light (hereinafter, external light is referred to as “h&ngr;”) is irradiated, holes are generated in an n-type substrate region
1406
of the n-type substrate
Hjerpe Richard
Lesperance Jean
Seiko Epson Corporation
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