Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Patent
1995-06-07
1996-02-20
Crane, Sara W.
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
257666, H01L 2302, H01L 23495
Patent
active
054931517
ABSTRACT:
Outer leads are buried in a package. At least the contact portions of the outer leads which are connected to a circuit board are exposed from the package and the exposed portions make the same flat surfaces as the package surface. When forming the package, the outer leads are used as the side wall of a mold forming mold, and therefore, they are formed thicker than inner leads inside the package. Thus, the package thickness can be made equal to the thickness of the outer leads.
REFERENCES:
patent: 5134458 (1992-07-01), Tsutsumi et al.
patent: 5299092 (1994-03-01), Yaguchi et al.
Asada Jun-ichi
Hori Masahiko
Takei Shinji
Clark Jhihan
Crane Sara W.
Kabushiki Kaisha Toshiba
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