Semiconductor device layout method capable of arranging function

Details Semiconductor device layout method capable of arranging function Semiconductor device layout method capable of arranging function

1997-03-03

1999-07-20

Teska, Kevin J.

Boots, shoes, and leggings

364490, G06F 1750

Patent

active

059263989

ABSTRACT:
A semiconductor device layout method arranges a given number of functional cells with regularity. In the layout method, a net list including circuit connection data necessary for the arrangement of the cells is read out, and then, the functional cells are divided into groups based on the net list and common data or control signals. Subsequently, an arranging order of the common data signals and the common control signals is determined, and then, the functional cells are rearranged per group based on the common data or control signals. Thereafter, a relative position list including relative positions of the rearranged functional cells is produced. Then, the functional cells are arranged based on read-out size data of the functional cells and the relative position list.

REFERENCES:
patent: 4882690 (1989-11-01), Shinsha et al.
patent: 5341308 (1994-08-01), Mendel
patent: 5566078 (1996-10-01), Ding et al.
patent: 5659717 (1997-08-01), Tse et al.
patent: 5661663 (1997-08-01), Scepanovic et al.
PTO 99-0248 (translation of Japanese Document No. 08-087533, published Apr. 2, 1996, filed Sep. 16, 1994, invented by Nakamura et al.).
PTO 99-0138 (translation of Japanese Document No. 05-152439, published Jun. 18, 1993, filed Nov. 27, 1991, invented by Hakoda et al.).

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