Semiconductor device layout method, a computer program, and...

Details Semiconductor device layout method, a computer program, and... Semiconductor device layout method, a computer program, and...

2011-08-23

2011-08-23

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

C716S110000, C716S111000, C716S119000

Reexamination Certificate

active

08006205

ABSTRACT:
A semiconductor device layout method is disclosed, wherein vias carrying the same signal are arranged at intervals equal to the minimum value defined by a design rule, and vias carrying different signals are arranged at second intervals that are greater than the minimum value.

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Dec. 24, 2008 official action in connection with a counterpart Japanese patent application No. 2003-200573.

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