Semiconductor device isolation structure and method of forming

Details Semiconductor device isolation structure and method of forming Semiconductor device isolation structure and method of forming

2002-06-20

2004-05-18

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S435000, C438S778000

Reexamination Certificate

active

06737333

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to the field of semiconductor devices and, more particularly, to a semiconductor device isolation structure and method of forming.
BACKGROUND OF THE INVENTION
Semiconductor devices are used in many electronic applications. One type of semiconductor device is a transistor. Manufacturers of transistors are continually reducing the size of transistors to increase their performance and to manufacture electronic devices in smaller sizes.
When many transistors are manufactured on a single integrated circuit die, oftentimes leakage current increases and breakdown voltage decreases, which severely degrades transistor performance. Manufacturers of transistors use isolation methods between transistors and other semiconductor devices to address these problems and others.
Shallow Trench Isolation (“STI”) is one method used for isolating transistors and other semiconductor devices. However, as transistor geometry shrinks, STI falls short of providing adequate isolation.
SUMMARY OF THE INVENTION
According to one embodiment of the invention, a method for isolating semiconductor devices includes forming a first oxide layer outwardly from a semiconductor substrate, forming a first nitride layer outwardly from the first oxide layer, removing a portion of the first nitride layer, a portion of the first oxide layer, and a portion of the substrate to form a trench isolation region, forming a second oxide layer in the trench isolation region, forming a spin-on-glass region in the trench isolation region, annealing the spin-on-glass region, removing a portion of the spin-on-glass region to expose a shallow trench isolation region, and forming a third oxide layer in the shallow trench isolation region.
Embodiments of the invention provide a number of technical advantages. Embodiments of the invention may include all, some, or none of these advantages. According to one embodiment, semiconductor device isolation is improved while eliminating a channel stop implant. This elimination reduces junction capacitance, resulting in faster devices. In that embodiment, such advantages are achieved without stringent lithographic alignment requirements.
Other technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.


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