Semiconductor device incorporating memory test pattern generatin

Details Semiconductor device incorporating memory test pattern generatin Semiconductor device incorporating memory test pattern generatin

1985-12-18

1987-10-20

Atkinson, Charles E.

Excavating

324 73R, 371 27, G01R 3128

Patent

active

047019190

ABSTRACT:
In a semiconductor device comprising a memory cell array and a test pattern generating circuit, the test pattern generating circuit generates the test pattern and transmits the test pattern to the memory cell array when receiving the least significant bit signal of address signals supplied to the memory cell array and the control signal.

REFERENCES:
patent: 3924181 (1975-12-01), Alderson
patent: 4519078 (1985-05-01), Komonytsky
patent: 4541090 (1985-09-01), Shiragasawa
Konemann et al., Built-In Test for Complex Digital Integrated Circuits, IEEE Journal of Solid-State Circuits, vol. SC-15, No. 3, Jun. 1980, pp. 315-319.
Fasang, Circuit Module Implements Practical Self-Testing, Electronics, May 19, 1982, pp. 164-167.

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