Semiconductor device incorporating circuit for generating...

Details Semiconductor device incorporating circuit for generating... Semiconductor device incorporating circuit for generating...

2001-02-23

2002-09-10

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S153000, C327S161000

Reexamination Certificate

active

06448826

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device operating synchronously with an external clock input from an external source.
2. Description of the Background Art
In order to deal with demands of higher operating speed and larger data capacity for semiconductor devices, a technology has been employed, in which a plurality of semiconductor devices mounted on one system are collaboratively operated in synchronization with each other for efficient entire operation.
In such a system, each semiconductor device is required to perform an instructed internal operation synchronously with a clock signal common to the entire system (hereinafter also referred to as an external clock signal).
Therefore, a semiconductor device in which synchronous operation is required generally includes a control clock generating circuit for generating an internal control clock (hereinafter also simply referred to as a control clock) for controlling operations of internal circuits at a timing synchronous with the external clock.
FIG. 27
is a block diagram showing a configuration of a conventional control clock generating circuit
300
. Control clock generating circuit
300
generates control clocks ISG
1
and ISG
2
synchronously with an external clock CLK.
Referring to
FIG. 27
, control clock generating circuit
300
includes a flip-flop
310
taking in a command signal CMD to generate a command clock CLKM in response to an activation timing of external clock CLK, and a pulse generating circuit
320
generating a reference clock pulse CLKP activated for a certain period in response to an activation of command clock CLKM.
Command signal CMD is activated when a command is provided to a semiconductor device including control clock generating circuit
300
. Thus, command clock CLKM output from flip-flop
310
is updated in its signal level for each activation timing of external clock CLK, and is activated to a high level in a clock cycle in which a command is provided. As to signal levels of a clock and a control signal, high level and low level are hereinafter indicated as H level and L level respectively.
FIG. 28
is a circuit diagram showing a configuration of a pulse generating circuit
320
.
Referring to
FIG. 28
, pulse generating circuit
320
includes a delay stage
322
for delaying command clock CLKM, and a logic gate
324
outputting a result of AND logical operation between an output of delay stage
322
and command clock CLKM as reference clock pulse CLKP.
Delay stage
322
includes an odd number of inverters. Delay stage
322
delays command clock CLKM by a delay time Th corresponding to the number of the inverters. This makes reference clock pulse CLKP a one shot pulse which is activated (to H level) for Th period in response to a transition of command clock CLKM from L level to H level. The activation period of a clock represented by the reference clock pulse is hereinafter also simply referred to as a pulse width.
Referring again to
FIG. 27
, reference clock pulse CLKP is fed to a delay circuit
330
. Delay circuit
330
includes a plurality of delay units
340
connected in series. Each delay unit
340
is constituted by, for example, identical inverters in a predetermined even number. An output of each delay unit is provided with a tap. Hereinafter, a reference character TP is used for generic indication of each tap, and a particular tap is denoted with subscripts, such as TPa, TPb and so forth.
Such a configuration allows reference clock pulse CLKP delayed stepwise by delay time tdf to be taken out by selecting tap TP. An output from each tap is amplified by a signal buffer
345
.
An internal control clock generating circuit
350
generates a control clock based on a signal taken in from each tap TP in delay circuit
330
. As an example of the control clock, ISG
1
and ISG
2
are representatively shown in FIG.
27
.
Internal control clock generating circuit
350
includes a logic gate
352
outputting an OR operation result of output signals of taps TPb and TPe. Logic gate
352
outputs control clock ISG
1
.
Internal control clock generating circuit
350
further includes a logic gate
354
outputting an OR operation result of output signals of taps TPa and TPd, a logic gate
356
outputting an OR logic operation result of output signals of taps TPc and TPf, and a logic gate
358
outputting an OR logical operation result of output signals of logic gates
354
and
356
. Logic gate
358
outputs control clock ISG
2
.
Thus, a control clock activated in response to an activation of the reference clock pulse can be generated by OR operation between a plurality of tap outputs whose activation periods overlapped with each other. If a number of tap outputs are used in generating the control clock having a relatively long pulse width such as control clock ISG
2
can be generated.
However, in a conventional control clock generating circuit
300
, the pulse width of reference clock pulse CLKP corresponds to a certain time period determined by the number of inverters constituting delay stage
322
. Further, a unit time tdf applied stepwise at delay circuit
330
also corresponds to a certain time period dependent on the number of inverters constituting delay unit
340
.
Therefore, when a semiconductor device on which control clock generating circuit
300
is mounted is applied to various systems, it may be difficult to generate a control clock corresponding to a change of an operating frequency, i.e., a period of external clock CLK.
FIGS. 29 and 30
are timing charts illustrating a problem of a conventional control clock generating circuit
300
corresponding to variation of the operating frequency, i.e., the period of external clock CLK.
FIG. 29
shows an example where the operating frequency is relatively low, that is, the period of external clock CLK is relatively long.
Referring to
FIG. 29
, the period of external clock CLK is T
0
. In a clock cycle in which a command is provided, reference clock pulse CLKP is activated for a certain time period Th in response to the activation of external clock CLK at time t
1
. Reference clock pulse CLKP is delayed stepwise per unit delay time tdf in delay circuit
330
, and is output from each tap TP.
Control signal ISG
1
is generated by logic gate
352
in response to a signal output from TPb and TPe of a plurality of taps TP provided at delay circuit
330
. An output of tap TPb rises to H level at time t
2
, and falls to L level at time t
4
. A difference of propagation delays between a leading edge and a trailing edge of a transistor in the delay unit may, as shown, make the interval between time t
2
and time t
4
longer than pulse width Th of reference clock pulse CLKP.
At t
3
preceding time t
4
, an output of tap TPe rises to H level. An output signal of tap Tb starts to fall after a certain time period Th from time t
3
, and changes to L level at time t
4
. As a result, control clock ISG
1
can be a control signal activated for a period from time t
2
to time t
5
in one clock cycle.
FIG. 30
shows an example where an operating frequency is relatively high, that is, a period of external clock CLK is relatively short.
Referring to
FIG. 30
, a period T
0
′ of external clock CLK is shorter than period T
0
of external clock CLK shown in. FIG.
29
. As in the case with
FIG. 29
, reference clock pulse CLKP is activated to H level for a certain period Th in response to an activation of external dock CLK at time t
1
in a clock cycle to which a command is applied.
Reference clock pulse CLKP is fed to delay circuit
330
as in the case with
FIG. 29
, and can output reference clock pulse CLKP delayed stepwise per unit delay time tdf at each tap of delay circuit
330
.
However, for pulse width Th of reference clock pulse CLKP and unit delay time tdf set at delay circuit
330
, the operating frequency, i.e., the period of external clock CLK is independent of variations, having the same value as the one in FIG.
29
. Thus, the fact that pu

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