Semiconductor device including three-dimensionally disposed logi

Details Semiconductor device including three-dimensionally disposed logi Semiconductor device including three-dimensionally disposed logi

1994-11-28

1996-05-14

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

257903, 257 72, 257225, 257904, 365181, 365188, H01L 27108

Patent

active

055170382

ABSTRACT:
Adjacent memory cells has a two-layer structure formed of first layer and second layer. The first layer is provided with driver transistors of the memory cell, access transistors of the memory cell, and driver transistors formed of the memory cell. The second layer is provided with load transistors of the memory cell, load transistors and of the memory cell, and access transistors of the memory cell. The transistors formed in the first layer are of an NMOS type, and the transistors formed in the second layer are of a PMOS type.

REFERENCES:
patent: 4805147 (1989-02-01), Yamanaka et al.
patent: 4852060 (1989-07-01), Rockett, Jr.
patent: 4902637 (1990-02-01), Kondou et al.
patent: 5001539 (1991-03-01), Inoue et al.
patent: 5057898 (1991-10-01), Adan et al.
patent: 5155058 (1992-10-01), Fujiwara et al.
patent: 5321286 (1994-06-01), Koyama et al.
patent: 5373170 (1994-12-01), Pfiester et al.
Hiroshi Okano et al., "Design of Optically Coupled Three-Dimensional Content Addressable Memory", Japanese Journal of Applied Physics, vol. 30, No. 3A, Mar., 1991, pp. L338-L341.

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