Active solid-state devices (e.g. – transistors – solid-state diode – With shielding
Reexamination Certificate
1998-12-01
2001-07-03
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
With shielding
C257S660000, C257S787000, C257S913000
Reexamination Certificate
active
06255719
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device capable of preventing a soft error caused by a neutron.
2. Description of the Background Art
Recently, in meetings of academic societies, articles or the like, various reports have been made on a soft error caused by a neutron in a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory) formed on a silicon substrate, for example by Ziegler et al. of IBM (International Business Machines Corp.) (J. F. Ziegler et al.,
J. Appl. Phys.,
52(6), 1981, p. 4305), Mckee et al. of TI (Texas Instruments Inc.) (W. R. Mckee et al.,
IRPS Proceedings,
1996, p. 1) and Tosaka et al. of Fujitsu (Y. Tosaka et al.
IEEE Trans. Nuel. Sci.,
Vol. 44, 1997, p. 173).
According to the reports, neutrons in a region with high energy level, specifically neutrons of about several tens of MeV or more react with silicon atoms and generate electric charges by elastic scattering or burst reaction. Then, electrons of the electric charges are collected to a storage node portion, so that the electric charges stored in a memory cell are changed and cell data is destroyed. This is a difficult problem to be solved because a larger number of electric charges are generated by the reaction as compared with a conventional soft error caused by an &agr;-particle.
Meanwhile, it has been predicted by Robert Baumann et al. of Japan TI (R. Baumann et al.
IRPS Proceedings,
1995, p. 297) that the soft error can be caused by reaction of
10
B included in a planarizing film before a metal interconnection of a device is formed and thermal neutrons (with energy level of about 0.05 eV) even in a region with neutrons of low energy level. A specific reaction formula is as follows.
10
B+n→&agr;(
1.471 MeV)+Li(839 KeV)+&ggr;(479 KeV)
The &agr;-particle or Li which is generated by the above mentioned reaction reacts with silicon to generate electric charges, whereby data is destroyed at a storage node. It is noted that
FIG. 11
is a schematic diagram shown in conjunction with generation of the electric charges caused by the above mentioned two types of reactions. In
FIG. 11
, a BPSG (Boro-Phospho Silicate Glass) layer
17
is formed on a silicon substrate
16
as a planarizing film including
10
B.
Although two types of the soft errors caused by neutrons have been reported as described above, the actual degrees of neutrons with different energy levels contributing to the soft error have been unknown. Then, the inventors of the present application manufactured two different types of SRAMs, one including
10
B in a planarizing film and the other without
10
B, and performed two types of experiments in the following.
In the first experiment,
252
Cf (californium) is used as a source of a neutron, covered with paraffin and converted to a thermal neutron, and directed to the SRAM. At the time, when a soft error ratio of the device including
10
B exceeds that of the device without
10
B, it is apparent that the soft error is caused by reaction of the thermal neutron and
10
B. As the result of the experiment showed a difference in soft error ratios of thirty times or more, it was found that the soft error is caused by the reaction of the thermal neutron and
10
B.
Next, as a second experiment, the degree of the influence of by thermal neutron on an energy distribution of neutrons in the nature was investigated. More specifically, a neutron acceleration experiment in high altitude flight was performed and contribution of each reaction was evaluated. It has been reported that 100 times or more neutrons exist in high altitude than on the ground (T. Nakamura, 1987, “Altitude Variation of Cosmic-Ray Neutron”,
Health Phys.
Vol. 53, p. 509.), so that evaluation can be made in a short period of time and while ignoring a soft error caused by a usual &agr;-particle. The result of the experiment showed that about half of the soft errors caused by neutrons are those caused by thermal neutrons. Thus, the inventors of the present application came to an conclusion that in solving the problem of the soft error, the thermal neutron is as important as the fast neutron which has conventionally been said as cause for soft error.
SUMMARY OF THE INVENTION
The present invention is made to solve the above mentioned problem. It is an object of the present invention to prevent a soft error caused by a thermal neutron.
According to one aspect, a semiconductor device of the present invention is provided with a package and a thermal neutron absorption sheet. In the package, a semiconductor chip internally having a storage element is included. The thermal neutron absorption sheet is applied on the surface of the package and includes a thermal neutron absorption material. Here, the thermal neutron absorption material is a material with a large absorption cross section for a thermal neutron such as
10
B.
By thus applying the thermal neutron absorption sheet on the surface of the package, the thermal neutron absorption material and the thermal neutron can be reacted inside the sheet. Thus, injection of the thermal neutron into the semiconductor chip and generation of electric charges in a silicon substrate can be prevented. In addition, as the thermal neutron absorber is formed in a sheet like shape, a large amount of thermal neutron absorption material can be added and the absorber can be made with a large thickness. This is effective for enhancing performance of absorbing not only a thermal neutron, but also a fast neutron.
The thermal neutron absorption sheet is preferably applied on the surface of the package through an adhesive. The adhesive preferably includes the thermal neutron absorption material.
As the thermal neutron absorption material is thus added to the adhesive, generation of electric charges caused by the thermal neutrons in the silicon substrate can be more effectively prevented.
According to another aspect, a semiconductor device of the present invention is provided with a package and a thermal neutron absorption layer. In the package, a semiconductor chip internally having a storage element is included. The thermal neutron absorption layer is provided inside the package and includes a thermal neutron absorption material.
Even when the thermal neutron absorption layer is thus provided, injection of a thermal neutron into the semiconductor chip can be prevented. Thus generation of electric charges in a silicon substrate is prevented.
According to still another aspect, a semiconductor device of the present invention is provided with a semiconductor chip and an &agr;-particle absorption layer having a thermal neutron absorption portion. The semiconductor chip is internally provided with a storage element. The &agr;-particle absorption layer is formed on the surface of the semiconductor chip, and the thermal neutron absorption portion includes a thermal neutron absorption material.
By thus providing the thermal neutron absorption portion in the &agr;-particle absorption layer, a thermal neutron is reacted inside the &agr;-particle absorption layer to generate an (x-particle or the like. As the energy of the &agr;-particle or the like can be lost inside the &agr;-particle absorption layer, injection of the &agr;-particle or the like into a silicon substrate is prevented. Thus, generation of electric charges in the silicon substrate is prevented.
The &agr;-particle absorption layers are preferably formed on upper and back surfaces of the semiconductor chip.
As a result, injection of the thermal neutron not only from the upper surface but also from the back surface of the semiconductor chip is prevented, so that generation of electric charges in the silicon substrate is effectively prevented.
The &agr;-particle absorption layer preferably has first and second &agr;-particle absorption portions. The first &agr;-particle absorption portion is positioned on the side of the semiconductor chip and does not include the thermal neutron absorption material. The second &agr;-particle absorption portion is formed
Akiyama Tatsuhiko
Arita Yutaka
Kishimoto Tadafumi
Kuriyama Hirotada
Tsutsumi Kazuhito
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Tran Minh Loan
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