Patent
1988-09-29
1990-07-24
Jackson, Jr., Jerome
357 38, 357 41, 357 13, H01L 2978, H01L 2974
Patent
active
049438352
ABSTRACT:
A zero-cross thyristor comprises an n-type substrate region surrounded by a p-type region, a p-type base region formed in the n-type substrate region and surrounding an n-type inner region of the n-type substrate region, and a p-type floating region formed in the n-type inner region. An n-channel MOS transistor whose gate is connected to the floating region is formed in the p-type base region. A first p.sup.+ -type diffusion region whose depth is less than that of the p-type base region is continuously formed in the p-type base region and the n-type inner region and a second p.sup.+ -type diffusion region whose depth is also less than that of the p-type floating region. The distance between the first and second diffusion regions is set to a predetermined value for preventing the breakdown of the gate insulating layer of the MOS transistor.
REFERENCES:
patent: 4492974 (1985-01-01), Yoshida et al.
patent: 4509067 (1985-04-01), Minami et al.
patent: 4602266 (1986-07-01), Coe
Japanese Patent Disclosure (KOKAI) No. 60-35571, "Semiconductor Device", Aug. 8, 1983, T. Suzuki et al.
Patent Abstracts of Japan, vol. 9, No. 212 (E-339) [1935], Aug. 29, 1985; & JP-A-60 74 678 (Toshiba K.K.) 26-04-1985.
Patent Abstracts of Japan, vol. 9, No. 154 (E-325) [1877], Jun. 28, 1985; & JP-A-60 35 571 (Sanken Denki K.K.) 23-02-1985.
Jitsukata Kouji
Yakushiji Shigenori
Jackson, Jr. Jerome
Kabushiki Kaisha Toshiba
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