Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2001-02-05
2002-11-05
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S203000
Reexamination Certificate
active
06477108
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly, relates to a system LSI (Large-Scale Integrated circuit) including a dynamic random access memory (DRAM).
2. Description of the Background Art
In recent years, a DRAM-mounted system LSI has been used which integrates a logic such as processor or ASIC (Application Specific Integrated Circuit) and a mass-storage DRAM on the same semiconductor substrate.
Such a system LSI interconnects the logic with the DRAM through a multi-bit internal data bus in the range from 128 bits to 512 bits, thereby enabling high-speed data transfer that is at least one order or two orders higher than that in the case where a logic LSI and a general-purpose DRAM having a small number of terminals are connected on a printed circuit board.
Moreover, the number of external pin terminals of the logic can be reduced as compared to the case where the general-purpose DRAM is externally connected to the logic.
Furthermore, within the system LSI, the DRAM block and the logic are connected through internal wiring. The internal wiling is short enough as compared to the wiring on the printed circuit board, and has small parasitic impedance. Therefore, a charging/discharging current of the data bus can be significantly reduced, and also high-speed signal transfer can be realized.
For these reasons, the DRAM-mounted system LSI significantly contributes to improved performance of the information equipments for conducting the processing handling a massive amount of data such as three-dimensional graphic processing and image/audio processing.
In developing such a DRAM-mounted system LSI, the DRAM block is supplied as DRAM core having a prescribed storage capacity. The system LSI is developed by arranging and interconnecting the combination of this DRAM core with another logic circuit, test circuit and analog circuit.
The DRAM core includes a memory array including a plurality of memory cells arranged in a matrix, and a control portion for generating a data-transmission/reception control signal based on a signal applied from the logic circuit or the like and applying the control signal to the memory array.
The control portion includes circuitry associated with command generation, row control and column control.
FIG. 23
is a block diagram showing the structure of a control portion
500
associated with command generation and row control in a DRAM core.
Referring to
FIG. 23
, control portion
500
includes a clock control circuit
522
for generating an internal clock signal int.CLK in response to a clock signal ext.CLK and a clock enable signal CKE, a timing signal generation circuit
524
for generating row timing signals RXT<
3
:
0
>, SO<
3
:
0
>and RXLATCH<
3
:
0
>corresponding to each bank in response to command signals ACT_CMD and PRE_CMD and a bank selection signal BS<
3
:
0
>, and a row address processing circuit
526
for outputting pre-decoded signals X
0
<
19
:
0
>to X
3
<
19
:
0
>to be output to each bank, in response to an address signal A<
12
:
0
>and the signal RXLATCH<
3
:
0
>. Note that, herein, the number of banks is four by way of example.
Clock control circuit
522
includes an internal clock generation circuit
530
for outputting the clock signal int.CLK from the clock signal ext.CLK in response to the clock enable signal CKE applied from a logic circuit or the like.
Timing signal generation circuit
524
includes a bank command generation circuit
534
for outputting command signals ACT<
3
:
0
>and PRE<
3
:
0
>corresponding to each bank in response to the bank selection signal BS<
3
:
0
>and based on the command signals ACT_CMD and PRE_CMD, and a row timing circuit
536
for outputting the row control timing signal RXT<
3
:
0
>of a main word line, the sense amplifier activation signal SO<
3
:
0
>, and the signal RXLATCH<
3
:
0
>that is activated during a row active period of the selected bank, in response to the command signals ACT<
3
:
0
>and PRE<
3
:
0
>. Each bit of the signals RXT<
3
:
0
>, SO<
3
:
0
>and RXLATCH<
3
:
0
>corresponds to each bank.
Row address processing circuit
526
includes a row address input latch circuit
540
for latching the address signal A<
12
:
0
>in response to the signal RXLATCH<
3
:
0
>to output row address signals RAF
0
<
12
:
0
>to RAF
3
<
12
:
0
>corresponding to the respective banks, and a row address pre-decode circuit
542
for outputting the pre-decoded signals X
0
<
19
:
0
>to X
3
<
19
:
0
>corresponding to the respective banks in response to the output of row address input latch circuit
540
.
The DRAM core generates an internal clock signal even during the standby period, resulting in large current consumption. Accordingly, like a synchronous dynamic random access memory (SDRAM) used as external component of, e.g., a CPU (Central Processing Unit), the DRAM core mounted in the system LSI also has a clock suspend function.
FIG. 24
is a circuit diagram showing the structure of internal clock generation circuit
530
of FIG.
23
.
Referring to
FIG. 24
, internal clock generation circuit
530
includes a CKE control circuit
552
for accepting the clock enable signal CKE in response to the external clock signal ext.CLK to output a clock control signal CKEd_P, and a gate circuit
554
for outputting the internal clock signal int.CLK from external clock signal ext.CLK in response to the clock control signal CKEd_P.
CKE control circuit
552
includes an inverter
556
for receiving and inverting the external clock signal ext.CLK, a flip-flop
558
for accepting the clock enable signal CKE in response to the external clock signal ext.CLK, a buffer circuit
560
for buffering the output of flip-flop
558
, and a flip-flop
562
for accepting the output of buffer circuit
560
in response to the output of inverter
556
.
Gate circuit
554
includes a NAND circuit
564
for receiving the external clock signal ext.CLK and the clock control signal CKEd_P, and an inverter
566
for receiving and inverting the output of NAND circuit
564
to output the internal clock signal int.CLK.
FIG. 25
is an operation waveform chart illustrating the clock suspend function.
Referring to
FIGS. 24 and 25
, in response to the fall of the clock enable signal CKE to L level at time t
1
, CKE control circuit
552
renders the clock control signal CKEd_P to L level from the following falling edge of the external clock signal ext.CLK. NAND circuit
564
responsively masks the external clock signal ext.CLK from time t
2
. Therefore, the internal clock signal int.CLK is fixed at L level, and the DRAM core is set to a powerdown mode.
In response to the rise of the clock enable signal CKE from L level to H level at time t
3
, supply of the internal clock signal int.CLK to each bank is resumed from time t
4
.
More specifically, by deactivating the clock enable signal CKE, the internal clock signal int.CLK is stopped one cycle thereafter, thereby entering the power-down mode. For an increased power-down mode period, the memory cell data in each bank is self-refreshed by asynchronously operating self-refresh circuits (not shown) in order to retain the data.
In response to activation of the clock enable signal CKE, the power-down mode is terminated and generation of the internal clock signal int.CLK is resumed one cycle thereafter.
In the conventional internal clock generation circuit, while the clock enable signal CKE is active at H level, the internal clock signal is continuously generated in response to the external clock signal. Particularly in the multi-bank structure, row local control circuits are provided corresponding to the respective banks, and a local clock signal for controlling an address latch circuit in each row local control circuit is generated in response to the internal clock signal, resulting in large current consumption involved in generation of the internal clock signal. Accordingly,
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