Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2002-08-15
2003-12-30
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S332000, C257S346000, C257S387000
Reexamination Certificate
active
06670711
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a semiconductor device having a self-aligned contact (SAC) structure.
2. Description of the Background Art
With recently increasing integration level and operating speed of semiconductor devices, there has been a demand for size reduction of an interconnection structure for connection between semiconductor devices. Reductions in distance between interconnect lines and in distance between contacts for connection between an interconnect line and an underlying semiconductor device have become accordingly important. Formation of such fine contacts requires high position accuracy in the patterning of contact holes. This position accuracy is determined by the accuracy of pattern alignment (or registration) in an exposure apparatus. Therefore, improving the accuracy of pattern alignment is a significant challenge.
There is a self-aligned contact (SAC) technique which is a process technique of contact hole formation for increasing the integration level of semiconductor devices while taking into account the insufficient accuracy of pattern alignment of the state-of-the-art exposure apparatus.
FIGS. 17A through 17H
are sectional views showing the steps of manufacturing a background art semiconductor device disclosed in Japanese Patent Application Laid-Open No. 11-87652 (1999). Specifically, the steps of forming contacts using the self-aligned contact technique in a DRAM memory cell are shown in
FIGS. 17A through 17H
.
First, isolators
102
are formed in a P-type semiconductor substrate
101
. Then, a gate oxide film
103
, an N-type polycrystalline silicon film and a silicon nitride film are deposited and patterned, whereby a gate electrode
106
of a MOS transistor and an on-gate nitride film
107
are formed. Next, using the on-gate nitride film
107
and the gate electrode
106
as a mask, phosphorus ions are implanted to form a first impurity diffused region
104
and a second impurity diffused region
105
which serve as source/drain regions (FIG.
17
A).
A silicon nitride film is deposited over the substrate, and is then anisotropically etched to form gate sidewall nitride films
109
(FIG.
17
B).
Next, a first interlayer insulation film
110
is deposited, and the upper surface of the first interlayer insulation film
110
is flattened by a CMP planarization process. Then, contact windows extending respectively to the first and second impurity diffused regions
104
and
105
are formed in the first interlayer insulation film
110
. An N-type polycrystalline silicon film is deposited over the substrate, and part of the N-type polycrystalline silicon film which overlies the first interlayer insulation film
110
is removed by a CMP process. This forms first and second plugs
111
and
112
(FIG.
17
C).
Then, an under-interconnect insulation film
113
made of silicon oxide is deposited on the first interlayer insulation film
110
and the first and second plugs
111
,
112
. Thereafter, a photoresist film is formed on the silicon oxide film
113
, the photoresist film having an opening over the first plug
111
for connection to the first impurity diffused region
104
. Using the photoresist film as a mask, etching is performed to form a contact window
114
extending to the first plug
111
(FIG.
17
D).
A tungsten film and a silicon nitride film are deposited in the order named on the substrate, and are then patterned. This forms a bitline
115
for connection to the first plug
111
and an on-bitline nitride film
116
(FIG.
17
E).
A silicon nitride film is deposited on the substrate, and is then anisotropically etched. This forms bitline sidewall nitride films
117
on the side surfaces of the bitline
115
and the on-bitline nitride film
116
(FIG.
17
F).
A second interlayer insulation film
118
made of silicon oxide is deposited, and the upper surface of the second interlayer insulation film
118
is flattened by a CMP planarization process. Then, a contact window extending to the second plug
112
is formed in the second interlayer insulation film
118
and the silicon oxide film
113
. An N-type polycrystalline silicon film is deposited over the substrate, and part of the N-type polycrystalline silicon film which overlies the second interlayer insulation film
118
is removed by a CMP process. This forms a third plug
119
for connection to the second plug
112
(FIG.
17
G).
A ruthenium film is deposited using a sputtering process and is then patterned to form a storage electrode
120
. Next, a BST film and a ruthenium film are deposited in the order named using a CVD process and are then patterned. This forms a capacitor film
121
and a plate electrode
122
(FIG.
17
H).
If the gate sidewall nitride films
109
and the on-gate nitride film
107
are exposed in the contact windows when forming the contact windows in the step shown in
FIG. 17C
, the above-mentioned method of manufacturing a DRAM memory cell can maintain a sufficiently high etch selectivity between the silicon oxide film and the silicon nitride film to reliably prevent the gate electrode
106
from being exposed by the removal of the on-gate nitride film
107
and the gate sidewall nitride films
109
. In other words, the method can prevent a short circuit between the first and second plugs
111
,
112
and the gate electrode
106
.
Similarly, if the bitline sidewall nitride films
117
and the on-bitline nitride film
116
are exposed in the contact window when forming the contact window in the step shown in
FIG. 17G
, the method can reliably prevent the bitline
115
from being exposed by the removal of the on-bitline nitride film
116
and the bitline sidewall nitride films
117
. In other words, the method can also prevent a short circuit between the third plug
119
and the bitline
115
.
As described in the above example, in the method of manufacturing a semiconductor device using the self-aligned contact technique, the silicon nitride films are used as the overlying films and sidewalls of the gate electrode
106
and the bitline
115
. This prevents the sidewalls and the like from being etched, if the opening area of the contact windows when formed overlaps the gate electrode
106
and the bitline
115
or their sidewalls and the like, because of the etch selectivity between the oxide film and the nitride film. Thus, the contact windows are defined in a self-aligned manner by the widths of the sidewalls
109
of the lower gate electrode
106
and the sidewalls
117
of the bitline
115
. There is no need to take into consideration a misalignment between patterns in the exposure step which accompanies the patterning of contact holes. In other words, the method using the self-aligned contact technique can reduce a margin for the pattern alignment even if the exposure apparatus has insufficient accuracy of pattern alignment, to contribute to the increase in integration level of the semiconductor device.
As described above, the self-aligned contact technique uses the etch selectivity between the oxide film constituting the interlayer insulation films and the nitride film. For this reason, the background art semiconductor device having the self-aligned contact structure has the nitride films provided around the gate electrode and the interconnect line. However, since the nitride film has a high dielectric constant and the relative dielectric constant of the nitride film is about 7 (whereas the relative dielectric constant of the oxide film is about 3.9), the semiconductor device having the self-aligned contact structure has an increased parasitic capacitance between gate electrodes and interconnect lines. This increase in capacitance is a serious hindrance to the reduction in power consumption and the increase in operating speed of the semiconductor device. Furthermore, since a decreasing spacing between the interconnect lines results in an abrupt increase in the capacitance between the interconnect l
Fujinaga Masato
Kunikiyo Tatsuya
Huynh Andy
Renesas Technology Corp.
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