Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2002-03-06
2004-05-04
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S209000, C257S529000, C365S096000, C365S225700, C337S401000
Reexamination Certificate
active
06731005
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-061443, filed Mar. 6, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a highly integrated semiconductor device, and in particular, to a semiconductor device which includes fuses for relieving defective areas in the semiconductor device.
2. Description of the Related Art
In a semiconductor device whose high integration is proceeding, reduction in circuit design rule is adopted as requirement of scaling down of the device. In a semiconductor device whose large scale integration is proceeding such as a DRAM in particular, a tendency of reduction in the circuit design rule is significant. In accordance with scaling down of the device, a redundancy technique in which an defective area is relieved by substituting the defective area with a redundant circuit provided in advance is widely utilized.
In actuality, it is difficult to produce a product without defective memory cells. Namely, it is difficult to produce normal memory cells for all bits. In an ordinary semiconductor storage device, defective memory cells are identified by a die sorting test and then the defective memory cells are substituted by redundant portions.
As an increase in capacity of semiconductor device proceeds, the number of defective bits increases. Also, the number of fuses for relieving the defective bits increases. In order to maintain a certain manufacturing yield rate, a predetermined number or less of the defective bits must be relieved by the fuses. At least several hundreds defective bits must be relieved by the fuses.
For example, a large capacity DRAM, about 10,000 fuses are provided in a semiconductor device. If a storage capacity of the device is increased twice with the same design rule, a chip area is increased twice. Thus, physical effects on memory cells caused by small dusts or foreign matters become significant. As a result, the number of defective bits is increased. Further, scaling down of the device proceeds, more elements are covered by the same dusts so as to be defective. Consequently, the number of defective bits increases.
In a fuse circuit for substituting the defective memory cells with the redundant circuit, fuses corresponding to the defective portions must be blown out. To blown out the fuses, laser is irradiated onto specified fuses and then only the specified fuses are blown out.
FIGS. 6A and 6B
show conventional fuses in a perspective manner. In
FIG. 6A
, eight fuses, i.e., first through eighth fuses
50
,
51
,
52
,
53
,
54
,
55
,
56
and
57
are shown. In contrast to a state shown in
FIG. 6A
,
FIG. 6B
shows a state in which laser is irradiated onto specified fuses. In
FIG. 6B
, the first fuse
50
, the third through fifth fuses
52
,
53
,
54
and the seventh fuse
56
have a thickness at a time of being formed, i.e., an initial thickness. These fuses are used with their storage state “1” stored therein.
In
FIG. 6B
, portions without fuse materials at laser irradiated portions in the second fuse
51
, the sixth fuse
55
and the eighth fuse
57
, i.e., a second fuse removed portion
58
, a sixth fuse removed portion
59
and an eighth fuse removed portion
60
refer to portions that fuses are removed by laser irradiation. These fuses are used with their storage state “0” stored therein. Here, “1” state is stored in the five fuses
50
,
52
,
53
,
54
and
56
. On the other hand, “0” state is stored in the three fuses
51
,
55
and
57
having the fuse removed portions
58
,
59
and
60
, respectively. In total, the eighth power of 2, i.e., 256 bits are stored in the device.
It is considered that the area of fuses is reduced by reducing a size of the fuse. However, because of a limit to a precision of focal position of laser irradiation in a laser blow device used for blowing fuses is provided of a constraint in spot diameter of laser light, it is difficult to set the fuse so as to be narrower than a certain width. Thus, the area of fuses cannot be further reduced.
FIGS. 1 through 6
in Jpn. Pat. Appln. KOKAI Publication No. 2000-340757 disclose a nonvolatile semiconductor storage device which has a high resistance element between a bit line and a drain, in which a plurality of resistance values are set by changing a width or length of the element at a time of design. However, a semiconductor device which uses a fuse whose resistance value can be changed after the design and in a final stage of manufacturing process of the device is not disclosed.
There arise problems in conventional semiconductor devices.
In accordance with an increase in storage capacity and proceeding of scaling down of the device, an area of fuses for relieving increasing defective bits must be enlarged. As a result, a ratio of the fuse area with respect to a chip becomes large. Since a large number of fuses are provided in the semiconductor device, an area of fuses which occupies the device is presently about 0.4%. In the future, further increase in capacity and scaling down of the device proceed, and a ratio of the fuse area may increase.
Since the number of bits to be relieved increases in accordance with an increase in capacity, the above-described problem becomes more serious. In a near future, the fuse area may be a factor which prevents compactness of chip. Further, if compactness of chip is prevented, a yield of semiconductor device per semiconductor wafer is decreased such that a manufacturing cost per chip is increased. Accordingly, reduction in the area of fuses must be needed in order to realize an increase in capacity.
Further, binary, i.e., “0” or “1” is conventionally stored by determining whether or not fuses are blown out. For this reason, if an amount of information to be stored in the fuse is increased, the number of fuses is increased. In this case, when the number of fuses are increased, as described above, the ratio of fuse area which occupies the semiconductor device is increased.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided a semiconductor device comprising:
a semiconductor substrate with which a circuit element is provided an insulating layer which is provided on said semiconductor substrate and has a concave portion; a first conductive line layer which is provided at said concave portion in said insulating layer and has a first thickness; and a second conductive line layer which is provided at said concave portion in said insulating layer so as to be formed apart in a horizontal direction from said first conductive line layer and has a second thickness which is smaller than the first thickness.
According to another aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate with which a circuit element is provided; an insulating layer which is provided on said semiconductor substrate and has a concave portion; and a conductive line layer made of N layers (wherein N is an integer of 2 or larger) which is provided at said concave portion in said insulating layer, with each layer having the same width, length and thickness, and its resistance value being successively smaller toward the bottom layer.
According to a further aspect of the present invention, there is provided a semiconductor device comprising a semiconductor substrate with which a circuit element is provided an insulating layer which is provided on said semiconductor substrate and has a concave portion; a first fuse which is provided at said concave portion in said insulating layer and is formed by laminating K fuse layers with different resistance values (wherein K is an integer of 2 or larger); and a second fuse which is provided at said concave portion in said insulating layer so as to be spaced apart from said first fuse, with its end portion having the same laminated structure as that of said first fuse, and its layers from the top
Fukuda Koichi
Koyama Hajime
Hogan & Hartson LLP
Kabushiki Kaisha Toshiba
Nelms David
Tran Mai-Huong
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