Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With semiconductor element forming part
Reexamination Certificate
1997-10-03
2003-04-29
Wille, Douglas A. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With semiconductor element forming part
Reexamination Certificate
active
06555901
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 8-264642 filed on Oct. 4, 1996, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device including an eutectic bonding portion and a method for manufacturing the same. For example, the present invention is favorably applied to a semiconductor device having a protection cap for covering a functional element therein.
2. Description of Related Art
Conventionally, a semiconductor acceleration sensor, a yaw rate sensor, or the like generally has a movable portion (vibrating portion) on its silicon chip. The movable portion is displaced in accordance with a physical quantity such as an acceleration, and an electric signal corresponding to the physical quantity is determined by converting the displacement of the movable portion to the electric signal. Also, in such a semiconductor device, as disclosed in JP-A-5-326702, a cap covers the movable portion in order to protect the movable portion. In this case, to improve the measurement sensitivity, stability of characteristics, avoidance of air damping, etc., it is preferable that an atmosphere around the movable portions is an inert gas atmosphere, a deoxidation gas atmosphere, or a vacuum atmosphere in some cases. Because of this, there is a need to seal the movable portion in the above-mentioned atmosphere, and therefore a cap for covering the movable portion without causing leakage therefrom is required.
To comply with this need, JP-A-5-326702 discloses a cap for covering not only an element having a movable portion but a chip carrying the element. However, this structure is not suitable for a device having a size which is to be miniaturized. Further, JP-A-4-304679 proposes a technology in which an element is sealed by a thin film formed during a wafer process. In this case, because the thin film serves as a cap, several disadvantages arise such that the mechanical strength thereof is low, the shape of the element is limited, there is no flexibility, and the like. To improve the mechanical strength thereof, a cap made of a bulk can be disposed on the chip in place of the cap made of a thin film. In this case, however, there is a need to invent a bonding method considering a quantity production property.
As a bonding method, anode bonding, direct bonding, and eutectic bonding methods are well known. In the anode bonding method, a high voltage is applied to the chip. If the chip has a circuit element, a withstand voltage of which is not so high, the circuit element is liable to be broken. To avoid this problem, the circuit element may be disposed on another chip other than the chip to which the cap is bonded. That is, the anode bonding method cannot be applied to the chip having the circuit element, and therefore there is no flexibility. In addition, gas is liable to be generated in the anode bonding process thereby adversely affecting sensing properties. Especially, in a vacuum sealing structure, the gas deteriorates the degree of vacuum. In the direct bonding method, there is a necessity to obtain adhesion at an atomic level. Therefore, this bonding method is generally applied to very limited cases. Further, this bonding method requires flat surfaces to be bonded and the application of high pressure. In view of the above, the direct bonding method is also difficult to be applied for the cap to be bonded to the chip.
In the eutectic bonding method that is a long-employed bonding method, the bonding portion is liquidized so that it does not require high pressure applied thereto.
Specifically, in a case where gold (Au) and silicon (Si) is bonded to each other in the eutectic bonding method (Au/Si eutectic bonding method), its bonding temperature is comparatively low and there is consistency between the bonding method and the other processes. Therefore, the eutectic bonding method is considered to be the most effective method for the bonding of the cap.
However, this bonding method has a disadvantage of being liable to produce voids in the bonding portion which may cause leakage therefrom. Now, there is no report about a technique that a void-less bonding is realized with a high yield in the eutectic bonding method. In addition, in the Au/Si eutectic bonding method, because silicon is an extremely active material, a naturally oxidized layer is formed on the surface of silicon. This oxidized layer disturbs an eutectic region to be formed on an entire interface between silicon and gold layers thereby resulting in large variations in bonding strength.
SUMMARY OF THE INVENTION
In view of the above-mentioned problems, an object of the present invention is to provide a semiconductor device including a Au/Si eutectic bonding portion which can solve the problems caused by a naturally oxidized layer of silicon and a method for manufacturing the same.
A semiconductor device according to the present invention includes first and second substrates bonded together by an eutectic portion of silicon and gold (Au/Si eutectic portion) containing an oxide of metal that has deoxidized silicon oxide.
In a method for manufacturing a semiconductor device according to the present invention, firstly, a first wafer having a silicon portion on a surface thereof and a second wafer having a gold layer and a metallic layer formed on a surface thereof are prepared. The metallic layer is made of metal having a deoxidizing property relative to silicon oxide. Then, in a state where the first and second wafers contacts each other, the first and second wafers are heated up to a temperature equal to or higher than an Au/Si eutectic temperature, thereby bonding to each other. Then, the first and second wafers are cut into individual semiconductor devices.
During the heating of the first and second wafers, metal of the metallic layer deoxidizes a naturally oxidized layer formed on a surface of the silicon portion of the first wafer. As a result, because the gold layer and the silicon portion can be contacted at an entire interface between the first and second wafers, an Au/Si eutectic portion is formed at all portion between the first and second wafers. Accordingly, variations of bonding strength between the first and second wafers are reduced, so that uniform and stable bonding can be realized. The metallic layer may be made of one material selected from titanium, aluminum, tantalum, zirconium, and niobium. The thickness of the metallic layer is preferably in a range of 10 nm to 100 nm. A protection layer made of gold may be formed on the metallic layer to prevent oxidization of the metallic layer. However, if the heating of the first and second wafers is performed in an atmosphere of vacuum, an inert gas, or deoxidization agent, the oxidization of the metallic layer can be prevented. In such a case, there is no need to form the protection layer on the metallic layer. To promote an eutectic reaction during the heating of the first and second wafers, it is effective to roughen a surface of the silicon portion in advance of the bonding of the first and second wafers.
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Nagakubo Masao
Ohara Fumio
Yoshihara Shinji
Brunson M.
DENSO Corporation
Harness Dickey & Pierce PLC
Wille Douglas A.
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