Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2000-01-20
2004-07-20
Pham, Long (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S750000, C257S759000, C257S758000
Reexamination Certificate
active
06765294
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device including multi-layered wiring layers connected by a via contact structure and a method for manufacturing such a semiconductor device.
2. Description of the Related Art
As semiconductor devices have been become more finely structured, multi-layered wiring layers have also become fine. Simultaneously, a via contact structure for connecting one wiring layer to another has also become finer.
On the other hand, in order to improve the manufacturing yield, a dual-damascene structure has been developed. According to this dual-damascene structure, a via contact structure and an upper wiring layer are simultaneously formed.
In a prior art method for manufacturing a semiconductor device including a dual-damascene structure, a first insulating layer is formed on a lower wiring layer, and an upper wiring mask layer having an opening is formed on the first insulating layer. Then, a second insulating layer is formed on the upper wiring layer, and an upper wiring pattern layer is formed on the second insulating layer. In this case, the upper wiring pattern layer has an opening with a width larger than a width of the opening of the upper wiring mask layer. Then, the first and second insulating layers are etched by using the upper wiring pattern layer as a mask to create a via hole and an upper wiring groove in the first and second insulating layers, respectively. Then, a conductive layer is buried in the via hole and the upper wiring groove, so that a first part of the conductive layer buried in the via hole serves as a via contact structure and a second part of the conductive layer buried in the upper wiring groove serves as a lower wiring layer. This will be explained later in detail.
In the above-described prior art method, however, since the width of the via contact structure is smaller than the width of the upper wiring layer, the contact area between the via contact structure and the upper wiring layer is so small as to increase the resistance therebetween. As a result, the current density of a current flowing through the via contact structure is increased to generate electromigration therein, which would disconnect the via contact structure. Thus, the reliability is deteriorated.
Also, in the above-described prior art method, if the second insulating layer is made of silicon oxide, it is difficult to form the upper wiring pattern layer due to the recess portion of the second insulating layer. In order to avoid this difficulty, an additional flattening process such as a chemical mechanical polishing (CMP) process can be performed upon the surface of the second insulating layer which, however, would increase the manufacturing cost.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device including a dual-damascene structure capable of decreasing the resistance between a via contact structure and its upper wiring layer.
Another object of the present invention is to provide a method for manufacturing such a semiconductor device.
According to the present invention, a first insulating layer is formed on a lower wiring layer having a via hole. Then, an upper wiring mask layer having an opening opposing the via hole is formed on the first insulating layer. The width of the opening is larger than that of the via hole. Then, a second insulating layer having an upper wiring groove whose width coincides with the via hole is formed on the upper wiring mask layer. Then, a via contact structure and an upper wiring layer are simultaneously buried in the via hole and the upper wiring groove, respectively. Since the width of the via contact structure is the same as that of the upper wiring layer, the contact area therebetween is increased.
Also, the second insulating layer is made of fluid coating material, so that it is easy to form the upper wiring pattern layer due to there being no recess portion of the second insulating layer.
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patent: 6054769 (2000-04-01), Jeng
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Hayes & Soloway P.C.
NEC Electronics Corporation
Pham Long
Trinh (Vikki) Hoa B.
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