Semiconductor device including dual damascene interconnections

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration

Reexamination Certificate

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C257S758000, C257S751000, C257S752000, C257S761000, C257S762000, C257S763000, C257SE21570, C257SE21020, C438S233000

Reexamination Certificate

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10853492

ABSTRACT:
A method (and structure) of forming an interconnect on a semiconductor substrate, includes forming a relatively narrow first structure in a dielectric formed on a semiconductor substrate, forming a relatively wider second structure in the dielectric formed on the semiconductor substrate, forming a liner in the first and second structures such that the first structure is substantially filled and the second structure is substantially unfilled, and forming a metallization over the liner to completely fill the second structure.

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patent: 6284642 (2001-09-01), Liu et al.
patent: 6313003 (2001-11-01), Chen
patent: 6319813 (2001-11-01), Givens
patent: 6319821 (2001-11-01), Liu et al.
S. Wolf, Silicon Processing for the VLSI ERA-2, 1990, p. 194.

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