Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-02-24
2001-04-03
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S233500
Reexamination Certificate
active
06212126
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, and particularly to a semiconductor device including a clock generation circuit that generates an internal clock in synchronization with a reference clock.
2. Description of the Background Art
Personal computers and work stations include a memory to store data. Among the memories, a DRAM (Dynamic Random Access Memory) that can read out and write data in large capacity is known to be used as the main memory for personal computers and work stations. Recently, a DDR SDRAM (Double Data Rate Synchronous Random Access Memory) is beginning to be used as the main memory for a work station.
This DDR SDRAM operates in synchronization with an externally applied clock signal. The DDR SDRAM includes a DLL (Delay Locked Loop) circuit to generate an internal clock signal in synchronization with an externally applied clock signal. The circuit in the DDR SDRAM operates in synchronization with this internal clock signal.
FIG. 16
shows a conventional DLL circuit disclosed in, for example, Japanese Patent Laying-Open No.11-120769. When an internal clock signal CLK
1
in synchronization with a clock pulse ECLK is to be generated using this conventional DLL circuit, there is a possibility that the pulse will disappear during the passage through a delay line if the pulse width of clock pulse ECLK is small.
SUMMARY OF THE INVENTION
An object of present invention is to generate an internal clock signal stably in a semiconductor device by appropriately controlling the pulse width of the clock pulse input to the delay line of a DLL circuit.
According to an aspect of the present invention, a semiconductor device includes a clock generation circuit generating an internal clock. The clock generation circuit includes a first pulse generator receiving a reset clock signal and a first reference clock signal that repeats a first transition from a first level to a second level and a second transition from the second level to the first level, and generating a first pulse signal that is set in response to the first transition and reset in response to a predetermined level transition of the reset clock signal, and a delay circuit receiving an input clock signal according to the first pulse signal to output an internal clock signal. The delay circuit includes a plurality of delay stages connected in series to output a reset clock signal from a delay stage between the first and last delay stages.
According to another aspect of the present invention, a semiconductor device includes a clock generation circuit generating an internal clock. The clock generation circuit includes a phase comparator circuit comparing phases between a first reference clock signal that repeats a first transition from a first level to a second level and a second transition from the second level to the first level and an internal clock signal, a delay control circuit providing a delay control signal according to the comparison result generated from the phase comparator circuit, a first pulse generator generating a first pulse signal set in response to the first transition of the first reference clock signal and reset at an elapse of a delay time controlled by the delay control signal, and a variable delay circuit receiving an input clock signal driven in response to the first pulse signal to output an internal clock signal delayed in response to the delay control signal.
Therefore, the main advantage of the present invention is that an input clock signal of an appropriate pulse width can be obtained since the pulse signal generated from the pulse generator is reset by a reset clock signal from one of the delay stages in the delay circuit.
Also, an input clock signal of an appropriate pulse width can be obtained since the pulse width of the pulse signal generated from the pulse generator is controlled by the variable delay circuit responding to a delay control signal. Therefore, an internal clock signal of the semiconductor device can be generated stably.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5740123 (1998-04-01), Uchida
patent: 5883534 (1999-03-01), Kondoh et al.
patent: 5940344 (1999-08-01), Murai et al.
patent: 5946268 (1999-08-01), Iwamoto et al.
patent: 6122215 (2000-09-01), Ohsawa
patent: 9-321614 (1997-12-01), None
patent: 10-69769 (1998-03-01), None
patent: 11-120769 (1999-04-01), None
Auduong Gene N.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
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