Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
1997-12-11
2003-02-25
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S738000
Reexamination Certificate
active
06525422
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device including bump electrodes, a manufacturing method and a testing method of the same, and also relates to a liquid crystal display device, a circuit substrate and a tape carrier package (hereinafter referred to as TCP), respectively, including the semiconductor device.
BACKGROUND OF THE INVENTION
Known methods of electrically connecting a semiconductor device to a liquid crystal display device, a circuit substrate or a TCP include a wireless bonding method wherein a bump electrode is provided on an electrode terminal of a semiconductor device, and the semiconductor device is bonded directly to the liquid crystal display device, the circuit substrate or the TCP using the bump electrode.
A concrete example will be given through the case of the liquid crystal display device of a chip-on-glass (hereinafter referred to as COG) method wherein a liquid crystal driver chip as a semiconductor device is directly face-down-bonded to a liquid crystal panel. The described COG method is classified into two types: (i) a paste COG method wherein the liquid crystal driver chip and the liquid crystal panel are connected by means of an electrically conductive paste; and (ii) an ACF-COG method wherein the liquid crystal driver chip and the liquid crystal panel are connected by means of an anisotropic electrically conductive film (hereinafter referred to as ACF).
As shown in FIG.
13
(
a
), a liquid crystal driver chip A′ includes a semiconductor base
101
whereon an insulating film
102
, an electrode pad
103
, and a protective film
104
with an opening are laminated in this order. On the opening, a bump electrode
106
is formed via a barrier metal
105
. On the other hand, a liquid crystal panel B′ on which the described liquid crystal drive chip A′ is to be bonded includes a glass substrate
109
whereon a conductive pattern
110
and a protective film
111
are laminated in this order.
In the paste COG method, after a conductive paste
112
is applied to the bump electrode
106
of the liquid crystal driver chip A′, the liquid crystal driver chip A′ is face-down-bonded to the liquid crystal panel B′. Then, the conductive paste
112
is cured, thereby connecting the bump electrode
106
and input and output terminals of the conductive pattern
110
.
On the other hand, in the ACF-COG method, as shown in FIG.
13
(
b
), an ACF composed of a binder resin
107
and conductive particles
108
is enclosed in a spacing formed between the liquid crystal driver chip A′ and the liquid crystal panel B′, thereby connecting the bump electrode
106
and the input and output terminals of the conductive pattern
110
via the conductive particles
108
.
However, the described COG method wherein the liquid crystal driver chip is directly face-down-bonded to the liquid crystal panel has a drawback in that a mounting inferior occurs when mounting the panel due to a bump inferior such as a bump defect, irregularity in bump height, etc.
Moreover, in the COG method, as the bump electrode is bonded to a hard material such as glass, etc., irregularity in height of bumps within the liquid crystal driver chip would cause a problem. For example, in the case of the ACF-COG method, the conductive particles in the ACF has an average particle diameter in a range of from 3 to 5 &mgr;m, and thus if a gap between heights of the adjoining bump electrodes is larger than the diameter of the conductive particle, an inferior connection occurs. Also, in the case of the paste COG method, if a gap between heights of the adjoining bump electrodes is larger than the thickness of the paste to be applied, an inferior connection occurs.
When adopting the COG method, in order to prevent an increase in a contact resistance, or contact due to an unexpected bump defect, a multiple port structure is generally adopted for the power source terminal and the input terminal. For the output terminal, however, in consideration of a space required, etc., the multiple port structure is not adopted.
Therefore, even when only one of the bump electrodes on the output terminal is defective, or significantly lower than the adjoining bump electrode (by not less than a conductive particle diameter), a panel display defect such as a line defect, etc., occurs, or fixing of the defective bump electrode is required or is discarded.
The described problem occurs not only in the liquid crystal display device of the COG method but also in the circuit substrate wherein the semiconductor chip is face-down-bonded to the substrate main body such as a print substrate, a ceramic substrate, etc. Such problem occurs because the substrate main body to which the bump electrode is bonded is made of a hard material.
The TCP has advantageous features over other face-down-bonding method in that (i) the inner lead is flexible, and (ii) an eutectic crystal is generated by the bump electrode and (Tin) plated onto the inner lead, and the inner lead is inserted into the bump electrode. However, even for the described TCP, for example, if a bump defect occurs, or a significant gap in bump height is generated, an inferior connection cannot be avoided.
In order to counteract the described problem, as shown in
FIG. 14
, Japanese Unexamined Utility Model Publication No. 56136/1991 (Jitsukaihei 3-56136) discloses a bonding bump wherein four divided gold bumps (bump electrodes)
206
a
,
206
b
,
206
c
and
206
d
are formed on a square connection terminal (electrode pad) 206. According to the described arrangement, a semiconductor chip is bonded to a substrate terminal by means of a curing resin around the metal bump. Therefore, by dividing the metal bump into four, an occurrence of an inferior connection due to residual resin remaining between (a) the metal bumps
206
a
,
206
b
,
206
c
and
206
d
, and (
b
) the substrate terminal can be avoided.
However, the described arrangement of Japanese Unexamined Utility Model Publication No. 56136/1991 has a drawback in that as the bump electrode is divided bidirectionally along a column and a row, narrowing of an electrode pad pitch, i.e., a wiring pitch, is not possible.
Moreover, the arrangement wherein the bump electrode composed of a transferred bump substrate is directly bonded to the semiconductor chip like the case of the above Gazette cannot be applied when the electrode pad pitch is not more than 100 &mgr;m. Recently, as an electrode pad pitch of 50 to 80 &mgr;m has been generally adopted to meet a demand for a miniaturization of a semiconductor chip, the described method cannot be used in practical applications.
The described mechanism is the same as the following mechanism. The generally used transfer bump adopts an inner lead bonding method wherein the bump electrode is transferred to a leading end of the inner lead of the tape carrier, and the bump electrode thus transferred is inner-lead-bonded to the electrode pad of the semiconductor chip. Although this method has an advantageous feature that a wafer bump process can be omitted, a mechanical connection is repeated twice, thus it is not practical to use the method for the electrode pad pitch of not more than 100 &mgr;m in view of precision. Therefore, in consideration of the fact that a mechanical connection is required, and the described transferring of the bump electrode can be performed only chip by chip, a wafer bump method wherein the bump electrode is formed on the electrode pad of the semiconductor chip in the wafer bump process is superior to the transfer bump method in view of both precision and mass production.
As to the divided bump electrodes, Japanese Unexamined Patent Publication No. 13418/1993 (Tokukaihei 5-13418) and Japanese Unexamined Patent Publication No. 58112/1995 (Tokukaihei 7-58112) disclose four divided bump electrodes for the purpose of suppressing a generation of a thermal stress.
However, neither of described Gazettes teach two divided bump electrodes or a mounting structure which offers a lower rate of inferior results such a
Chikawa Yasunori
Inohara Akio
Kanda Makoto
Nie Norimitsu
Ono Atsushi
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