Active solid-state devices (e.g. – transistors – solid-state diode – Schottky barrier – With means to prevent edge breakdown
Reexamination Certificate
2002-06-07
2003-12-30
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Schottky barrier
With means to prevent edge breakdown
C257S483000, C257S481000, C257S480000, C257S488000, C257S471000, C257S104000, C257S106000, C257S077000
Reexamination Certificate
active
06670688
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device requiring a high breakdown voltage.
2. Description of the Background Art
It is important that a semiconductor device constituted to block a high voltage by a pn junction is to relieve an electric field strength of a junction surface provided in contact with a substance having a different dielectric constant and is to stably implement a breakdown voltage as designed as compared with a junction electric field strength in a silicon substrate.
For this reason, a field limiting ring structure, an SIPOS (Semi-Insulating Polycrystalline Silicon) structure and the like have generally been used as a junction termination processing structure.
<SIPOS Structure>
FIG. 13
shows a sectional structure of a silicon diode
80
having an SIPOS structure as a junction termination processing structure.
As shown in
FIG. 13
, the silicon diode
80
comprises a p-type impurity layer
202
provided as an operation region of the diode and containing a p-type impurity in a relatively high concentration (p
+
), and a p-type impurity layer
208
having a part thereof overlapping with an edge portion of the p-type impurity layer
202
and containing the p-type impurity extended in a horizontal direction toward an outer peripheral portion in a relatively low concentration (p
−
) in one of main surfaces of a silicon substrate
201
containing an n-type impurity in a relatively low concentration (n
−
).
The p-type impurity layer
208
has a 3-step shape. The steps overlap each other and have the whole shape such that a junction depth and a concentration are reduced toward the outer periphery. The p-type impurity layer
208
is provided to surround the p-type impurity layer
202
on a plane.
A maximum depth of the p-type impurity layer
208
is 20 &mgr;m in a device having a breakdown voltage of 1.2 kV and 70 &mgr;m in a device having a breakdown voltage of 5 kV, for example. Moreover, the p-type impurity layer
202
has a depth of 5 to 40 &mgr;m.
An anode electrode
204
is provided on the p-type impurity layer
202
and an SIPOS film
206
is provided from an upper part of the p-type impurity layer
208
to an upper part of the outer peripheral portion, and a silicon nitride film (Si
3
N
4
)
207
is provided on the SIPOS film
206
.
The SIPOS film
206
has a thickness of 500 &mgr;m and contains 10% of oxygen, for example. Moreover, the silicon nitride film
207
has a thickness of 150 nm.
An n-type impurity layer
203
containing an n-type impurity in a relatively high concentration (n
+
) is provided in the other main surface of the silicon substrate
201
and a cathode electrode
205
is provided on the n-type impurity layer
203
.
Thus, the p-type impurity layer
208
having the 3-step shape is provided to surround the operation region of the diode. Therefore, a depletion layer DL is extended during the operation of the device so that an electric field of a pn junction portion can be relieved and a breakdown voltage can be maintained.
In the case in which a backward voltage is applied to the silicon diode
80
, a current flows to the SIPOS film
206
so that the SIPOS film
206
can stabilize an electric field distribution of the semiconductor substrate
201
.
Moreover, the silicon nitride film
207
functions as a protective film, thereby contributing to stable maintenance of the breakdown voltage.
Next, a method of forming the p-type impurity layer
208
will be described with reference to FIG.
14
. As shown in
FIG. 14
, the p-type impurity layer
202
is formed in one of the main surfaces of the silicon substrate
201
and a resist mask RM is then subjected to patterning on the main surface of the silicon substrate
201
.
The resist mask RM has such a pattern that an opening OP
1
having a large area corresponding to an area of the deepest diffusion layer is provided on the same diffusion layer in the p-type impurity layer
208
having three steps, and a plurality of openings OP
2
are provided on two other diffusion layers and the number of the openings OP
2
is decreased when a diffusion depth is reduced.
By using the resist mask RM having such a structure for an ion implantation mask, an effective implantation amount can be changed for each diffusion layer and the p-type impurity layer
208
having the 3-step shape can be obtained by thermal diffusion after ion implantation.
<Field Limiting Ring Structure>
Next, a sectional structure of a silicon carbide diode
90
having a field limiting ring structure as a junction termination processing structure will be described with reference to FIG.
15
.
Since silicon carbide has a greater energy gap between bands than that of silicon, it has a great thermal stability so that a silicon carbide device can be operated at a high temperature of 1000 K (Kelvin) or less. In addition, the silicon carbide has a high thermal conductivity. Therefore, the silicon carbide device can be provided at a high density.
Moreover, the silicon carbide has a breakdown electric field which is approximately ten times as great as that of silicon. In a conduction blocking state, therefore, the silicon carbide is suitable for a device to be operated on a condition that a high voltage might be generated.
On the other hand, the SIPOS structure has a great temperature dependency. In the silicon carbide diode having a large operating temperature range, therefore, there is a possibility that a voltage blocking capability might be extremely changed at low and high temperatures. Consequently, it is not desirable that the SIPOS structure should be applied to the silicon carbide diode. For this reason, the field limiting ring structure is generally applied to the silicon carbide diode.
As shown in
FIG. 15
, in the silicon carbide diode
90
, an n-type epitaxial layer
303
containing an n-type impurity in a relatively low concentration (n
−
) is provided on one of main surfaces of a silicon carbide substrate
301
containing the n-type impurity in a relatively high concentration (n
+
).
The n-type epitaxial layer
303
takes a step shape having a protrusion PP and a base bottom portion BP, and a p-type impurity layer
302
containing a p-type impurity in a relatively high concentration (p
+
) and acting as an operation region of the diode is provided in a surface of the protrusion PP.
A side surface of the protrusion PP is constituted such that a side surface of the n-type epitaxial layer
303
has an inclination with respect to a pn junction interface of the n-type epitaxial layer
303
and the p-type impurity layer
302
. Thus, a bevel structure is obtained.
A silicon oxide film
307
is provided from the side surface of the protrusion PP from which a junction end of the pn junction is exposed to a surface of the base bottom portion BP, and the junction end is not directly exposed.
Moreover, the base bottom portion BP is selectively provided with a p-type impurity layer
308
containing a p-type impurity in a relatively low concentration (p
−
) to surround the protrusion PP, thereby constituting a field limiting ring. The field limiting ring is set in a floating state.
An anode electrode
304
is provided on the p-type impurity layer
302
and a cathode electrode
305
is provided on the other main surface of the silicon carbide substrate
301
.
Since the field limiting ring
308
is thus provided to surround the operation region of the diode, a high breakdown voltage can be implemented. More specifically, when a backward bias is applied to the diode
90
, a depletion layer is first formed around a main junction. When the backward bias is increased, the depletion layer is extended toward the outer peripheral side and the main junction and the field limiting ring punch through before avalanche breakdown of the main junction is caused. Consequently, a maximum field effect of a curved portion of the main junction can be relieved and a breakdown voltage can be maintained.
A me
Satoh Katsumi
Suekawa Eisuke
Loke Steven
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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