Electricity: conductors and insulators – Boxes and housings – Hermetic sealed envelope type
Reexamination Certificate
2000-05-11
2002-05-21
Dinkins, Anthony (Department: 2831)
Electricity: conductors and insulators
Boxes and housings
Hermetic sealed envelope type
C174S260000, C361S760000, C361S764000
Reexamination Certificate
active
06392145
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor devices and, more particularly, to semiconductor devices housed in array packages having terminals arranged about surfaces of the packages.
2. Description of the Related Art
Following fabrication, an integrated circuit (IC) is typically housed in a protective semiconductor device package. As IC fabrication technology improves, manufacturers are able to integrate more and more functionality into a single IC. As the number of integrated functions increases, so do the number of signal lines which need to be connected to external devices. Accordingly, IC manufacturers are shifting from peripheral-terminal packages, with terminals arranged around a periphery of the package, to array semiconductor device packages having terminals arranged about an underside surface of the package. The physical dimensions of array device packages having hundreds of terminals are much smaller than their peripheral-terminal counterparts.
FIG. 1
is a bottom plan view of an exemplary semiconductor device
10
employing a pin grid array (PGA) device package housing an IC. The PGA package includes a substrate
12
having multiple conductive pins
14
extending outwardly from an underside surface of substrate
12
. Pins
14
are provided for connecting to a printed circuit board (PCB) or for inserting into a socket. As is typical, pins
14
are arranged about an outer portion of the underside surface of the PGA package.
FIG. 2
is a cross-sectional view of semiconductor device
10
as indicated in FIG.
1
. As illustrated in
FIG. 2
, semiconductor device
10
includes an IC
16
coupled to substrate
12
and a cover or lid
18
. IC
16
is mounted upon a center portion of an upper surface of substrate
12
using the well known controlled collapse chip connection (C
4
) or “flip chip” method. Multiple solder bumps connect a set of I/O pads on a frontside surface of IC
16
to corresponding bonding pads on the upper surface of substrate
12
. A layer
20
of a thermal interface material thermally couples a backside surface of IC
16
to an underside surface of lid
18
.
Substrate
12
includes multiple horizontal layers of electrical conductors in a stacked arrangement. The electrical conductors connect pins
14
to bonding pads on the upper surface of substrate
12
. Adjacent layers are electrically isolated from one another by a dielectric material used to form substrate
12
. Vertical conductive vias connect electrical conductors in different layers. One or more of the horizontal layers may be patterned to form trace conductors. Signals are routed to and from IC
16
via trace conductors.
A portion of pins
14
and corresponding electrical conductors within substrate
12
are used to provide electrical power to IC
16
. For example, in
FIG. 2
, a pin
14
A and a horizontal conductor
22
A may be used to supply a first reference “ground” power supply voltage to a bonding pad
24
A of substrate
12
. Similarly, a pin
14
B and a horizontal conductor
22
B may be used to supply a second power supply voltage (e.g., a “positive” power supply voltage) to a bonding pad
24
B of substrate
12
.
Magnitudes of power supply voltages tend to decrease as the dimensions of electronic devices formed upon IC substrates decrease. On the other hand, power supply current magnitudes tend to increase as the number of electronic devices placed on ICs increase, and as the operating frequencies of the electronic devices increase. Resistances along power supply current paths between pins
14
and bonding pads
24
of substrate
12
cause IR voltage drops in the power supply voltage, where I is the magnitude of power supply current flowing along a path and R is the electrical resistance along the path.
A problem arises in that the current carrying abilities of individual pins
14
are limited, and the relatively long power supply current paths within substrate
12
result in relatively large IR voltage drops. Due to the limited current carrying abilities of individual pins
14
, the size of the portion of pins
14
dedicated to providing electrical power to IC
16
is typically substantial. In
FIG. 2
, power supply currents flowing through pins
14
A-
14
B and corresponding horizontal conductors
22
A-
22
B encounter electrical resistances of pins
14
A-
14
B and horizontal conductors
22
A-
22
B. These electrical resistances cause IR voltage drops in the power supply voltage provided to IC
16
. As pins
14
are arranged about the outer portion of the underside surface of substrate
12
, and IC
16
is mounted upon the center portion of the upper surface of substrate
12
, the lengths of power supply current paths through horizontal conductors
22
are relatively long. The electrical resistance of a conductor is directly proportional to the length of the current path through the conductor. As a result, the electrical resistances of the horizontal conductors
22
are relatively high.
Further, when IC
16
transforms an appreciable amount of electrical energy into heat energy, substrate
12
is often formed from a ceramic material (e.g., aluminum oxide). Horizontal conductors
22
within ceramic substrates are typically formed from refractory metals (e.g., tungsten or molybdenum). Compared to other metals from which conductors are commonly formed, refractory metals have relatively high electrical resistivities. As the electrical resistance of a conductor is directly proportional to the electrical resistivity of the conductor, the electrical resistances of horizontal conductors
22
are typically greater in common ceramic substrates than in packages made from other materials. IR voltage drops along power supply current paths are thus greater in common ceramic substrates.
It would thus be desirable to have a semiconductor device package for housing an IC and having terminals for providing electrical power to the IC wherein the current carrying abilities of the terminals are greater than those of individual pins
14
. The desired terminals would be located near the IC to reduce IR voltage drops between the terminals and the IC.
SUMMARY OF THE INVENTION
A semiconductor device package, and a semiconductor device employing the package, are described. The semiconductor device package is intended for housing an integrated circuit (IC), and includes a substrate adapted to receive the IC. The substrate includes a surface (e.g., an underside surface) having an outer portion surrounding a center portion. A first group of signal terminals are arranged about the outer portion of the surface, and a second group of power supply terminals are arranged about the center portion. Placing the power supply terminals in the center portion of the surface reduces the lengths of power supply current paths within the substrate, thus reducing IR voltage drops within the substrate. The power supply terminals are made physically larger than the signal terminals such that the electrical resistances of the power supply terminals are lower than the electrical resistances of the signal terminals.
The group of power supply terminals may include at least one set of power supply terminals, wherein each power supply terminal of each set provides a different power supply voltage to the IC. For example, the IC may require two different power supply voltages—a first reference “ground” voltage, and a second “positive” voltage which is positive with respect to the reference ground voltage. In this case, the group of power supply terminals may include any number of pairs of power supply terminals. One power supply terminal of each pair provides the reference ground voltage to the IC, and the other power supply terminal provides the positive voltage to the IC.
The signal terminals and the power supply terminals may extend outwardly from the surface of the substrate, and may be adapted for coupling to either a printed circuit board or a socket contact. The signal terminals may be cylindrical and have circular cross sections. In contrast, each power supply terminal may have one or
Advanced Micro Devices , Inc.
Conley Rose & Tayon PC
Dinkins Anthony
Kivlin B. Noäl
Oliva Carmelo
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