Semiconductor device including alignment marks

Details Semiconductor device including alignment marks Semiconductor device including alignment marks

1997-02-27

1999-09-07

Kelley, Nathan K.

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

H01L 23544

Patent

active

059491450

ABSTRACT:
A fabrication method for a semiconductor device is provided, which is able to increase pattern-to-pattern lithography overlay accuracy. After a first layer made of a first material is formed, first and second slits serving as a first alignment mark are formed in the first layer. The first and second slits are spaced with a specific distance and are approximately parallel to each other. Each of the first and second slits is filled with a second material. Then, a second layer made of a third material is formed on the first layer. Subsequently, a mask is formed on the second layer. The mask has a first pattern serving as a second alignment mark. The second alignment mark is overlapped with the first and second slits serving as the first alignment mark. Preferably, the first alignment mark provides the main scale of a caliper, and the second alignment mark provides the vernier scale of the caliper.

REFERENCES:
patent: 5308682 (1994-05-01), Morikawa
patent: 5475268 (1995-12-01), Kawagoe et al.
patent: 5640049 (1997-06-01), Rostoker et al.

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