Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1997-06-18
2001-02-13
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S377000, C257S384000, C257S413000, C257S775000
Reexamination Certificate
active
06188136
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of wirings or electrodes of a semiconductor device and a method of making thereof, and more particularly to a semiconductor device and a method of making thereof that accelerates the speed of a semiconductor device by reducing capacitances of wirings, and minimizes facilitating redundant process steps.
2. Description of the Related Art
Conventionally, polycrystal silicon including impurities in high concentration is used for a material of a gate electrode and wirings for connecting elements of a MOSFET constituting a semiconductor device. However, with the acceleration of the speed of a semiconductor device in recent years, a laminated structure of polycrystal silicon including impurities in high concentration and a metal having a low resistance and a high melting point or silicides thereof has been used more frequently than polycrystal silicon alone including impurities in high concentration.
FIGS.
1
(
a
) and
1
(
b
) illustrate a structure of a semiconductor device constituted by MOSFETs using the silicide technology.
FIG.
1
(
a
) is a sectional view showing a semiconductor device manufactured by a conventional manufacturing method and FIG.
1
(
b
) is a plan view of patterns of portions essential for facilitating understanding of the sectional view shown by FIG.
1
(
a
). A section taken along a line I
A
—I
A
of FIG.
1
(
b
) corresponds to FIG.
1
(
a
).
With reference to FIG.
1
(
a
), the semiconductor device includes a P-type silicon substrate
1
, a P-type well
2
, an N-type well
3
and an element isolating insulating layer
4
. Further, in an order from the left in FIG.
1
(
a
), a single PMOS (P-type Metal Oxide Semiconductor), a PMOS and an NMOS (N-type Metal Oxide Semiconductor) constituting a CMOS (Complementary Metal Oxide Semiconductor) inverter in which a gate electrode is integrally formed by a local wiring on the element isolating insulating layer (hereinafter, well isolating insulating layer)
4
on a boundary between the P-type well
2
and the N-type well
3
, a single NMOS, a redundancy cut portion
15
, and a wiring on the element separating insulating layer
4
and single body of NMOS on a P-type well, are formed.
Source and drain regions, gate electrodes and the like are connected to aluminum wirings
13
on an inter-layer insulating film
12
through contact holes.
According to the conventional method of making a semiconductor device as illustrated, the P-type well
2
and the N-type well
3
are formed on the substrate
1
. Then, the element isolating insulating layer
4
is formed on the surface of the wells
2
and
3
by the LOCOS (Local Oxidation of Silicon) process or the STI (Shallow Trench Isolation) process. Next, thin thermally-oxidized films
5
as gate oxide films and polycrystal silicon portions
63
and
64
are successively formed. Next, the polycrystal silicon portions
63
and
64
are patterned by using lithography technology whereby gate electrodes and wirings are formed.
Next, N-regions
71
and P-regions
72
having a shallow diffusion depth are formed by ion-implanting impurities respectively into regions of the NMOSFET and the PMOSFET for forming sources and drains with the gate electrodes and a resist mask, not illustrated, serving as masks. Next, silicon nitride is formed all over the face and side walls
8
are formed on side faces of the gate electrodes by anisotropically etching silicon nitride. Next, impurities are again ion-implanted into regions for forming the sources and the drains with the gate electrodes formed with the side walls
8
and a resist mask, not illustrated, serving as masks. As a result, N+ regions
91
(source, drain regions) and P+ regions
92
(source, drain regions) having a deep diffusion depth are formed. Here, N− and P−designate low impurity concentration and N+ and P+ designate high impurity concentration.
Next, the gate insulating film
5
on the source and drain regions
91
and
92
of the N-type and the P-type MOSFETs, are removed and the respective source and drain regions
91
and
92
are exposed. Next, a high-melting point metal, for example, a titanium and a titanium nitride are continuously accumulated all over the face by a sputtering process. Next, heat treatment is carried out by which silicide layers
11
are formed. Unreacted titanium and titanium nitride are removed by etching.
The technology of forming a silicide layer self-aligningly on the surface of exposed silicon is referred to as SALICIDE (Self Aligned Silicide) technology.
Next, the inter-layer insulating film
12
is accumulated and the surface is flattened by a CMP (Chemical-Mechanical Polishing) process. Next, areas other than the openings of the contact holes are covered by a resist, not illustrated, and an anisotropic etching is carried out whereby a contact hole
19
extending toward the wiring and a contact hole
20
extending toward the diffusion layer are simultaneously opened. Thereafter, a high-melting point metal
18
such as tungsten or the like is selectively formed only at the opening portions of the contact holes
19
and
20
by using a CVD (Chemical Vapor Deposition) process. Next, the aluminum wirings
13
and a passivation film
14
are formed and the semiconductor device is completed after a pad step.
When the semiconductor device to be manufactured includes a memory, after the pad step, an etching is carried out on the passivation film
14
and the inter-layer insulating film
12
to a degree to form a shallow portion of the inter-layer insulating film
12
so that the redundancy cut portion
15
may be provided on the wiring comprising the polycrystal silicon portions
63
and the silicide layer
11
as shown by FIG.
1
(
a
).
According to the conventional method of making the MOSFET, in the step of ion-implanting the regions for forming sources and drains, the gate electrodes and the wirings on the P-type well
2
and the gate electrodes and the wirings on the N-type well
3
, are simultaneously ion-implanted.
Therefore, high concentrations of impurities are introduced into the polycrystal silicon portions
63
and
64
constituting the gate electrodes and the wirings, with the result that the gate electrodes and the wirings are formed to have high conductivity.
However, the following problems are caused when high concentrations of impurities are introduced into all of the polycrystal silicon portions.
That is, the wirings having constituent elements of the polycrystal silicon portions
63
and
64
which are formed on the element isolating insulating layer
4
and where high concentrations of impurities have been introduced, constitute the MIS (Metal Insulator Semiconductor) capacitance with respect to the surface of the wells via the element isolating insulating layer
4
. The MIS capacitance has a very large value since it is formed between the lower faces of the polycrystal silicon portions
63
and
64
and the surface of the P-type well
2
or the surface of the N-type well
3
. As a result, the capacitance of wirings is increased whereby high speed operation of the semiconductor device is hampered.
Further, when a voltage is applied on the wirings having the constituents of the polycrystal silicon portions
63
and
64
, an inversion layer is caused in the P-type well
2
or the N-type well
3
beneath the element isolating insulating layer
4
, whereby the function of the isolating elements may be lost.
Accordingly, the threshold voltage in causing such an inversion layer must be sufficiently higher than the operational voltage of the semiconductor device.
That is, in order to secure the function of isolating elements, the impurity concentration of the P-type well
2
and the N-type well
3
must be higher. However, thereby, the source-drain coupling capacitances that are formed between the source and the drain regions
91
and
92
, and the P-type well
2
and the N-type well
3
, are increased whereby high speed operation of the transistor is hampered.
A
Eckert II George C.
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Saadat Mahshid
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