Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2000-11-29
2003-02-25
Williams, Alexander O. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S685000, C257S723000, C257S730000, C257S777000, C257S778000, C257S737000, C257S738000, C257S700000, C257S701000, C257S754000, C257S691000, C257S692000, C257S668000, C361S760000, C361S763000, C361S762000, C361S803000, C361S807000, C361S808000, C361S809000, C361S767000
Reexamination Certificate
active
06525414
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device formed by mounting semiconductor elements on both sides of a wiring board having three-dimensional wiring which uses inner via holes.
2. Description of the Related Art
Attempts have been made to develop a semiconductor element in which a plurality of electronic circuits are incorporated in a single semiconductor element (for example IC chip, MIC chip and OEIC chip) in order to make electronic apparatuses having semiconductor elements used therein more compact. In practice, however, it is difficult to make a single semiconductor element having all necessary functions due to limitations related to semiconductor material, production process, design rule and other factors, and it is often necessary to use a plurality of semiconductor elements. In such a case, in order to make the device smaller in size and run at a higher speed, a chip-on-chip configuration is employed in which the semiconductor elements are directly connected with each other by of electrodes as shown in FIG.
19
. In the drawing, numeral
1
denotes a first semiconductor element,
2
denotes electrodes formed on the first semiconductor element
1
,
3
denotes a second semiconductor element,
4
denotes electrodes formed on the second semiconductor elements,
10
denotes junctions made mainly of an electrically conductive metallic material such as solder, and
11
denotes a cured insulating resin. When such a chip-on-chip configuration is employed, length of wiring between the semiconductor elements can be made shorter, transmission delay of electric signals is reduced, operation speed of the semiconductor device can be made faster and, because the semiconductor elements are mounted in laminated configuration, it is also possible to make the semiconductor device smaller.
If the first semiconductor element
1
and the second semiconductor element
3
are electrically connected via the junctions
10
in such a chip-on-chip configuration as described above, it is necessary to position the electrodes
2
,
4
of the semiconductor elements so that they oppose each other. For this reason, general-purpose semiconductor elements cannot be used and it is required to use semiconductor elements which are designed by taking the positions of the electrodes
2
,
4
into consideration. Consequently, it is impossible to design the semiconductor elements separately.
Also because the positions of the electrodes
2
,
4
of the first and the second semiconductor elements are restricted, it becomes difficult to reduce the size of the semiconductor device in some cases, eventually resulting in lower production yield.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device which is capable of operating at a higher speed and is smaller in size by employing general-purpose semiconductor devices without using the chip-on-chip configuration.
Particularly, an object of the present invention is to provide a semiconductor device capable of operating at a higher speed and is smaller in size. This is because the wiring length does not increase even when using semiconductor elements such as a CPU, wherein the electrodes are formed in an array arrangement. Although the examples below utilize a multi-layer wiring board, the objects discussed above can also be achieved by using a wiring board including a single insulation layer.
The present inventors have found that it becomes possible to produce semiconductor devices of smaller size while maintaining a high operating speed of the semiconductor elements by mounting general-purpose semiconductor elements so that they oppose each other via a multi-layer wiring board, in which both sides of the multi-layer wiring board has a three-dimensional wiring layout employing inner via holes for connecting electrodes of the semiconductor elements with each other. Particularly, the semiconductor device can be produced without making the wiring longer even when the semiconductor element has an area array type electrode arrangement by employing the three-dimensional wiring as described above. Thus, the present invention has been completed.
That is, the present invention provides a semiconductor device comprising a multi-layer wiring board having at least first and second semiconductor elements mounted on the respective sides of the multi-layer wiring board. Electrodes of the semiconductor element are connected with each other by the three-dimensional wiring. The multi-layer wiring board is made by laminating insulation layers, which comprise resin-impregnated fiber sheets and circuit pattern layers alternately, and has three-dimensional wiring for electrically connecting the circuit pattern layers provided on both sides of the insulation layer via a plurality of inner via holes that are provided through each of the insulation layers.
The semiconductor device according to the present invention can be made smaller in size in a configuration similar to chip-on-chip configuration by employing the general-purpose semiconductor elements because the semiconductor elements are mounted face down by flip chip bonding via the multi-layer wiring board of thin layers. Particularly because the three-dimensional wiring employing the inner via holes is used in the multi-layer wiring board, the semiconductor elements mounted on both sides of the multi-layer wiring board can be connected by the three-dimensional wiring. Therefore, it is possible to make the wiring shorter compared to a case where a conventional wiring board is used in which lead wires are arranged to run over the substrate surface in two-dimensional wiring.
Consequently, according to the present invention, it becomes possible to achieve a high operating speed of the elements by making the semiconductor device smaller in size so as to prevent a delay in electric signals from occurring by using a reduced wiring length. This is similar to the case of employing the conventional chip-on-chip configuration even when the general-purpose semiconductor elements are used.
Also, because the multi-layer wiring board is disposed between the semiconductor elements, the semiconductor element can be mounted or removed without causing a stress in the other semiconductor elements. Thus, it is possible to prevent the semiconductor elements from being damaged.
It is preferable that projections of one or more semiconductor element mounted on either surface of the multi-layer wiring board in a direction perpendicular to the multi-layer wiring board overlap each other.
When the semiconductor elements are mounted on the respective surfaces of the multi-layer wiring board so that projections thereof in a direction perpendicular to the multi-layer wiring board overlap each other, a potential of the multi-layer wiring board
107
to warp in the perpendicular direction (Z axis direction) can be reduced even in a case in which the insulating substrate constituting the multi-layer wiring board is made of a fiber sheet impregnated with a thermosetting resin which has a low rigidity and is liable to warp.
The present invention also provides a semiconductor device comprising first, second and third semiconductor elements laminated via the multi-layer wiring board. The multi-layer wiring board is bonded to cover the back surface of the second semiconductor element by bending the multi-layer wiring board whereon the first and the second semiconductor elements are mounted at specified positions on either side thereof. The third semiconductor element is mounted by flip chip bonding, so as to oppose the back surface of the second semiconductor element via the multi-layer wiring board.
When the multi-layer wiring board of thin layers is bent and the semiconductor device and the multi-layer wiring board are laminated alternately as described above, the semiconductor device can be made small in size even when a large number of semiconductor elements are mounted.
The present invention also provides a module for mounting semiconductor devices comprising th
Amami Kazuyoshi
Bessho Yoshihiro
Mitani Tsutomu
Shiraishi Tsukasa
Matsushita Electric - Industrial Co., Ltd.
Wenderoth , Lind & Ponack, L.L.P.
Williams Alexander O.
LandOfFree
Semiconductor device including a wiring board and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device including a wiring board and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device including a wiring board and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3173434