Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
1999-09-14
2004-05-11
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S374000, C257S903000
Reexamination Certificate
active
06734523
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device in which a well is divided into a plurality of parts by a trench, and a method of manufacturing the semiconductor device.
2. Description of the Background Art
Semiconductor devices are usually formed by using a p-type semiconductor substrate (e.g., silicon substrate). As shown in
FIG. 29
, a p-channel transistor pT (source drain regions RN are of n-type) may be formed on a p-type semiconductor substrate
900
, whereas in forming an n-channel transistor nT (source drain regions RP are of p-type), it is necessary to form a local n-type layer NW. The layer NW is called “well.”
Wells are generally classified as thermal diffusion well and retro-grade well. In forming a thermal diffusion well NW, impurity N is implanted into a shallow position in a semiconductor substrate
900
(see FIG.
30
), and the structure of
FIG. 30
is subjected to heat treatment at high temperature for a prolonged time, so that the impurity N is diffused into the semiconductor substrate
900
(see FIG.
31
), resulting in the thermal diffusion well NW. A retro-grade well MW is formed by implanting impurity N into a deep position in a semiconductor substrate
900
, as shown in FIG.
32
.
FIG. 33
shows the impurity concentration profile on the line A—A of FIG.
32
. Since the retro-grade well is formed by implanting the impurity N, the impurity concentration profile can be set arbitrarily. In
FIG. 33
it is controlled such that the impurity concentration has a maximum at a deep position P
1
in the semiconductor substrate
900
, and the impurity concentration at a shallow position P
2
in the substrate
900
is higher than that of the substrate
900
and sufficiently lower than that of the channel. This offers the merit that the transistor nT in the well NW is protected against the influence of the potential outside of the well NW.
In recent years, the decreased size of a transistor nT has created the need for increasing the impurity concentration of the well NW in order to suppress punch through. In some elements, therefore, a well NW is intentionally distributed so as to reach the main surface of a semiconductor substrate
900
for adjustment of the impurity concentration of the well NW.
Adjustment of impurity concentration is required to not only an n-channel transistor nT but also a p-channel transistor pT in some cases. In this case, a p-type well PW is formed (see FIG.
34
).
Further, if it is desired to arbitrarily set the substrate potential of the p-channel transistor pT (i.e., the potential of a back gate), the well PW is electrically isolated from other regions by an n-type bottom well BNW and a well NW, as shown in FIG.
35
.
When a well NW and a well PW are in contact with each other (see FIG.
36
), both wells can be electrically isolated by a depletion layer DR to be generated at the interface therebetween. This merit is to permit an easy electrical isolation between the well NW and the well PW. The depletion layer DR, however, has a tendency to extend and thus it might extend throughout a zone EUR. This causes the demerit that it is impossible to form a transistor in the zone EUR. An element isolation film Ta is formed in the zone EUR in which no transistor is formed (see FIG.
37
).
To overcome the above demerit, a trench is formed at the boundary between the well NW and the well PW, and an element isolation film Tb is buried in the trench (see FIG.
38
). Thereby, no depletion layer occurs at a well boundary between the well NW and the well PW (i.e., in the vicinity of the element isolation film Tb). This offers the merit that a transistor can be formed in the zone EUR by reducing the margin from the well boundary to a transistor. Unfortunately, the step of employing a trench is complicated and expensive which are the drawbacks of this step.
Two methods of well isolation using a trench are presently proposed. One comprises a first step of forming an element isolation film and a second step of forming n-type and p-type wells.
FIG. 39
shows a structure formed by this method. With this method, no disadvantages are caused by reducing the margin from a well boundary to an element, however, the well isolation process using a trench involves the above two steps. Accordingly, this method is time-consuming and increases the manufacturing cost.
The other is to conduct the above first and second steps at the same time.
FIG. 40
shows a structure formed by this method. The structure of
FIG. 40
is realized by forming a deep element isolation film Th such as to correspond to the depth of wells NW and PW (see FIG.
41
), or forming shallow wells NW and PW such as to correspond to the thickness of an element isolation film Th (see FIG.
42
), alternatively, in a combination of these. In any event, the depth of the element isolation films Tb is evened and each of the wells NW and PW is divided into a plurality of parts by the element isolation film Tb.
It is, however, necessary to open a contact
201
per active region, namely, per well (see FIG.
43
), in order to apply the desired potential to each of the isolated wells NW and PW. Thus it is necessary to increase the area of a well by the amount of a region CR for providing the contact
201
. That is, as a whole, it fails to take full advantage of the merit in terms of area that is obtained by the trench as stated earlier with respect to FIG.
38
. Also, there is a problem that layout area is increased by the amount of the region CR to be provided per well.
Accordingly, an object of the present invention is to provide a semiconductor device in which a well is divided into a plurality of parts by a trench, to effect a reduction in layout area, as well as a method of manufacturing the semiconductor device.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a semiconductor device comprises: a semiconductor substrate; an element isolation film formed such as to have to a predetermined depth from a main surface of the semiconductor substrate, the element isolation film dividing the area from the main surface to the depth into a plurality of first regions; first wells formed in the first regions, respectively; and a second well formed in a second region deeper than the first wells in the semiconductor substrate, the second well being in contact with some of the first wells.
According to a second aspect, the semiconductor device according to the first aspect is characterized in that the first and second wells of the first and second regions on one side with reference to a predetermined boundary are of a first conductivity type, and the first and second wells on the other side are of a second conductivity type.
According to a third aspect, the semiconductor device according to the second aspect is characterized in that the second well of the first conductivity type and the second well of the second conductivity type are not in contact with each other.
According to a fourth aspect, the semiconductor device according to the first aspect is characterized in that the second well is formed on only one side of the second region with reference to a predetermined boundary.
According to a fifth aspect, the semiconductor device according to the fourth aspect is characterized in that the second well is formed in a memory cell part in the second region.
According to a sixth aspect, the semiconductor device according to the first aspect is characterized in that the second well is formed only in the vicinity of the bottom of the element isolation film in the second region.
According to a seventh aspect, the semiconductor device according to the first aspect is characterized in that each impurity concentration of the first and second wells is higher as being closer to a boundary part between the first and second regions.
According to an eighth aspect, the semiconductor device according to the first aspect further comprises a third well formed in a third region deeper than the second region in the semiconductor substrate.
According to a nint
Oda Hidekazu
Ueno Shuuichi
Yamashita Tomohiro
Loke Steven
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Renesas Technology Corp.
LandOfFree
Semiconductor device including a well divided into a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device including a well divided into a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device including a well divided into a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3188484