Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2000-03-16
2003-09-02
Huynh, Kim (Department: 2182)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S054000, C361S111000
Reexamination Certificate
active
06614633
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a protecting circuit which is capable of preventing the semiconductor device from a rapid surge. The present invention is applicable to insulated gate transistors, such as power metal oxide semiconductor field effect transistors (abbreviated MOSFETs) and insulated gate bipolar transistors (abbreviated IGBTs).
FIG. 22
shows a conventional semiconductor device. A protecting apparatus of this conventional semiconductor device comprises a serial circuit
3
consisting of a plurality of clamping Zener diodes. The serial circuit
3
is connected between drain and gate electrodes of a double diffused metal oxide semiconductor (DMOS) field-effect transistor
2
which is actuated by a gate actuating circuit
8
. The purpose of providing the serial circuit
3
is to improve the surge durability against a surge voltage caused by an inductive load
1
.
According to the circuit arrangement shown in
FIG. 22
, when the semiconductor device receives a surge voltage applied from the inductive load
1
, each Zener diode in the serial circuit
3
causes breakdown at a predetermined voltage level lower than that of the field-effect transistor
2
. Thus, the field-effect transistor
2
turns on in response to electric charge input to the gate electrode thereof. Surge current, corresponding to the surge voltage, flows through the field-effect transistor
2
. In the following description, the field-effect transistor is referred to or abbreviated as FET.
As the operation resistance of FET
2
has a positive temperature coefficient, no current concentration occurs. Accordingly, FET
2
causes no internal breakdown. A parasitic transistor
2
a
of FET
2
does not operate. The surge durability of the semiconductor device is improved.
In this semiconductor device, each Zener diode in the serial circuit
3
may be a multiple polysilicon Zener diode including alternately doped boron and phosphor, or a multiple Zener diode formed by diffusing base and emitter layers in a power integrated circuit.
Thus, the Zener diodes are not large in chip size. The overall size of the Zener diodes is generally small compared with that of FET
2
.
The internal resistance of all Zener diodes in the serial circuit
3
is usually a large value equal to approximately 1 k&OHgr;. To allow the current to smoothly flow, it is necessary to maintain breakdown voltage of each Zener diode (which is usually 10V lower than the withstand voltage of FET
2
). Thus, a sufficiently large bias cannot be applied to the gate electrode of FET
2
. Hence, a current amount flowing in response to the turning-on operation of FET
2
is small. In other words, it is difficult to sufficiently improve the durability against a rapid and large-current surge caused by an electrostatic discharge (abbreviated ESD, hereinafter).
FIG. 23
shows a conventional semiconductor device proposed in the Unexamined Japanese patent publication No. 8-64812.
According to the circuit arrangement shown in
FIG. 23
, a protecting circuit
4
, a back-flow preventing Zener diode
5
and a resister
6
are connected between an inductive load
1
and the gate electrode of FET
2
.
The protecting circuit
4
includes a DMOS-FET
4
a.
This FET
4
a
has a drain electrode connected to a drain electrode of FET
2
and a source electrode connected via the Zener diode
5
and the resister
6
to the gate electrode of FET
2
.
Furthermore, the protecting circuit
4
includes a capacitor
4
b
which is connected between the gate and drain electrodes of FET
4
a.
The capacitor
4
b
is connected in parallel with a serial circuit which consists of a plurality of clamping Zener diodes
4
c
connected in series. A resister
7
is interposed between the gate and source electrodes of FET
4
a.
When a surge voltage caused by the inductive load
1
is applied to the protecting circuit
4
, the surge current passes the capacitor
4
a
and flows into the gate electrode of FET
4
a.
Thus, FET
4
a
turns on in the initial stage.
In response to the turning-on operation of FET
4
a,
the surge current based on the surge voltage caused by the inductive load
1
flows into the gate electrode of FET
2
via FET
4
a,
Zener diode
5
and the resister
6
, so as to turn on FET
2
. Thus, the surge current flows across FET
2
from the inductive load
1
.
However, when the surge voltage is an ESD surge causing rapid and large current (having operation time of approximately 10 nsec, peak current of approximately 160 A, 150&OHgr;, 150 pF, and 25 kV discharge), it is necessary to quickly increase the gate potential of FET
2
to a higher level (e.g., 10 times the threshold value of FET
2
) in a short time (e.g., within 1 nsec) by turning on FET
4
a.
When FET
2
turns on, the surge current flows across FET
2
.
However, as described above, the resister
6
is interposed between the Zener diode
5
and the gate electrode of FET
2
. The resister
6
limits the charge current flowing into the gate electrode of FET
2
. Thus, it becomes impossible to quickly and sufficiently charge the gate electrode of FET
2
.
Accordingly, there is the possibility that the internal diode of FET
2
induces avalanche breakdown. In a worst case, the parasitic bipolar transistor of FET
2
may operate and induce permanent damage due to current concentration. As a result, the ESD durability of FET
2
(or the semiconductor device) may deteriorate.
SUMMARY OF THE INVENTION
In view of the foregoing, an object of the present invention is to provide a protecting apparatus for a semiconductor device which is capable of surely protecting the semiconductor device from the rapid surge, such as ESD surge.
In order to accomplish this and other related objects, the present invention provides a protecting apparatus for protecting a main transistor formed on a semiconductor substrate from a rapid surge, comprising a back-flow preventing Zener diode having a cathode connected directly to a control terminal of the main transistor for preventing current from flowing in a predetermined direction, a protecting transistor having an output terminal connected to an anode of the back-flow preventing Zener diode and an input terminal connected to an input terminal of the main transistor, and a protecting capacitor connected between a control terminal of the protecting transistor and the input terminal of the main transistor for allowing initial surge current, when caused based on a rapid surge, to flow into the control terminal of the protecting transistor. The protecting transistor, when turning on in response to the initial surge current, allows next surge current succeeding the initial surge current to flow into the control terminal of the main transistor via the back-flow preventing Zener diode. And, the main transistor, when turning on in response to the next surge current, allows late surge current succeeding the next surge current to flow therethrough.
According to this arrangement, no resister is connected between the protecting transistor and the main transistor. Only the back-flow preventing Zener diode, having a small internal resistance value, is connected between the protecting transistor and the main transistor. Thus, the current amount of next surge current flowing through the protecting transistor is not limited or suppressed. The next surge current smoothly flows into the control terminal of the main transistor.
With this arrangement, the next surge current serving as charging current quickly and sufficiently flows into the control terminal of the main transistor. Hence, the main transistor turns on immediately without inducing the avalanche breakdown of the diode constituting a parasitic element or without activating the transistor constituting a parasitic element. The late surge current can smoothly flow through the main transistor. Thus, it becomes possible to improve the ESD durability of the semiconductor device.
The present invention provides another protecting apparatus for protecting a main transistor formed on a semicondu
Denso Corporation
Harness Dickey & Pierce PLC
Huynh Kim
LandOfFree
Semiconductor device including a surge protecting circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device including a surge protecting circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device including a surge protecting circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3102309