Semiconductor device including a signal generator activated...

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

Reexamination Certificate

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Details

C324S765010

Reexamination Certificate

active

07741862

ABSTRACT:
A mode decode/latch circuit decodes an input signal based on a latch timing signal to output a test mode signal to a test execution circuit. Test mode signal line includes a high-resistance portion extending from the mode decode/latch circuit toward the vicinity of the test execution circuit and a low-resistance portion connecting together the distal end of the high-resistance portion and the input of the test execution circuit. A latch circuit for latching the test mode signal based on the latch timing signal is inserted in the low-resistance portion.

REFERENCES:
patent: 5056094 (1991-10-01), Whetsel
patent: 5402063 (1995-03-01), Kim
patent: 6333879 (2001-12-01), Kato et al.
patent: 6559669 (2003-05-01), Sugamoto et al.
patent: 7457179 (2008-11-01), Cheon
patent: 06-177251 (1994-06-01), None
patent: 11-163065 (1999-06-01), None

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